÷
2, Differential-to-2.5V/3.3V
87332I-01
DATA SHEET
ECL/LVPECL Clock Generator
G
ENERAL
D
ESCRIPTION
The 87332I-01 is a high performance ÷2 Differential-to-2.5V/3.3V
ECL/LVPECL Clock Generator. The CLK, nCLK pair can accept
most standard differential input levels The 87332I-01 is characterized
to operate from either a 2.5V or a 3.3V power supply. Guaranteed
output and part-to-part skew characteristics make the 87332I-01
ideal for those clock distribution applications demanding well defined
performance and repeatability.
F
EATURES
• One ÷2 differential 2.5V/3.3V LVPECL / ECL output
• One CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• Maximum output frequency: 500MHz
• Maximum input frequency: 1GHz
• Translates any single ended input signal to 3.3V LVPECL
levels with resistor bias on nCLK input
• Part-to-part skew: 400ps (maximum)
• Propagation delay: 1.6ns (maximum)
• LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.8V, V
EE
= 0V
• ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -2.375V to -3.8V
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
B
LOCK
D
IAGRAM
CLK
nCLK
÷2
Q
nQ
P
IN
A
SSIGNMENT
MR
CLK
nCLK
nc
1
2
3
4
8
7
6
5
Vcc
Q
nQ
V
EE
MR
87332I-01
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
87332AMI-01 REVISION C 2/12/15
1
©2015
Integrated Device Technology, Inc.
87332AMI-01
DATA SHEET
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5
6, 7
8
Name
MR
CLK
nCLK
nc
V
EE
Q, nQ
V
CC
Input
Input
Input
Unused
Power
Output
Power
Type
Description
Master reset. When LOW, outputs are enabled. When HIGH,
Pulldown divider is reset forcing Q output LOW and nQ output HIGH.
LVCMOS / LVTTL interface level.
Pulldown Non-inverting differential clock input.
Pullup
Inverting differential clock input.
No connect.
Negative supply pin.
Differential output pair. LVPECL interface levels.
Positive supply pin.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
CLK
MR
Q
F
IGURE
1. T
IMING
D
IAGRAM
÷2, Differential-to-2.5V/3.3V
ECL/LVPECL Clock Generator
2
REVISION C 2/12/15
87332AMI-01
DATA SHEET
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5 V
50mA
100mA
112.7°C/W (0 lfpm)
-65°C to 150°C
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V, V
EE
= 0, T
A
= -40°C
TO
85°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
3.3
Maximum
3.8
30
Units
V
mA
T
ABLE
3B. LVCMOS DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V, V
EE
= 0, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
MR
MR
MR
MR
V
CC
= V
IN
= 3.8V
V
CC
= 3.8V, V
IN
= 0V
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
150
Units
V
V
µA
µA
T
ABLE
3C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V, V
EE
= 0, T
A
= -40°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input High Current
Input Low Current
CLK
nCLK
CLK
nCLK
Test Conditions
V
CC
= V
IN
= 3.8V
V
CC
= V
IN
= 3.8V
V
CC
= 3.8V, V
IN
= 0V
V
CC
= 3.8V, V
IN
= 0V
-5
-150
0.15
1.3
V
CC
- 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
Common Mode Input Voltage;
V
EE
+ 0.5
NOTE 1, 2
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is V
CC
+ 0.3V.
REVISION C 2/12/15
3
÷2, Differential-to-2.5V/3.3V
ECL/LVPECL Clock Generator
87332AMI-01
DATA SHEET
T
ABLE
3D. LVPECL DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V, V
EE
= 0, T
A
= -40°C
TO
85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
- 1.4
V
CC
- 2.0
0.65
Typical
Maximum
V
CC
- 0.9
V
CC
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50Ω to V
CC
- 2V.
T
ABLE
4. AC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V, V
EE
= 0, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
tsk(pp)
t
R
t
F
odc
Parameter
Input Frequency
Propagation Delay; NOTE 1
Part-to-Part Skew; NOTE 2, 3
Output Rise Time
Output Fall Time
Output Duty Cycle
20% to 80%
20% to 80%
200
200
49
ƒ
≤
1GHz
1.1
1.4
Test Conditions
Minimum
Typical
Maximum
1
1.6
400
700
700
51
Units
GHz
ns
ps
ps
ps
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
NOTE: All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
÷2, Differential-to-2.5V/3.3V
ECL/LVPECL Clock Generator
4
REVISION C 2/12/15
87332AMI-01
DATA SHEET
P
ARAMETER
M
EASUREMENT
I
NFORMATION
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
D
IFFERENTIAL
I
NPUT
L
EVEL
P
ART
-
TO
-P
ART
S
KEW
P
ROPAGATION
D
ELAY
O
UTPUT
R
ISE
/F
ALL
T
IME
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
REVISION C 2/12/15
5
÷2, Differential-to-2.5V/3.3V
ECL/LVPECL Clock Generator
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