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HY57V64420HG

Description
4 Banks x 4M x 4Bit Synchronous DRAM
File Size139KB,11 Pages
ManufacturerSK Hynix
Websitehttp://www.hynix.com/eng/
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HY57V64420HG Overview

4 Banks x 4M x 4Bit Synchronous DRAM

HY57V64420HG
4 Banks x 4M x 4Bit Synchronous DRAM
DESCRIPTION
The Hynix HY57V64420HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which
require large memory density and high bandwidth. HY57V64420HG is organized as 4banks of 4,194,304x4.
HY57V644020HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-
nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by
a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of read
or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or
write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
Single 3.3±0.3V power supply
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin
pitch
All inputs and outputs referenced to positive edge of system
clock
Data mask function by DQM
Internal four banks operation
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No.
HY57V64420HGT-5/55/6/7
HY57V64420HGT-K
HY57V64420HGT-H
HY57V64420HGT-P
HY57V64420HGT-S
HY57V64420HGLT-5/55/6/7
HY57V64420HGLT-K
HY57V64420HGLT-H
HY57V64420HGLT-P
HY57V64420HGLT-S
Clock Frequency
200/183/166/143MHz
133MHz
133MHz
100MHz
100MHz
200/183/166/143MHz
133MHz
133MHz
100MHz
100MHz
Power
Organization
Interface
Package
Normal
4Banks x 4Mbits x4
LVTTL
400mil 54pin TSOP II
Low power
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of
circuits described. No patent licenses are implied.
Rev. 0.4/Nov. 01
1

HY57V64420HG Related Products

HY57V64420HG HY57V64420HGT-H HY57V64420HGT-P HY57V64420HGT-S HY57V64420HGLT-K HY57V64420HGLT-H
Description 4 Banks x 4M x 4Bit Synchronous DRAM 4 Banks x 4M x 4Bit Synchronous DRAM 4 Banks x 4M x 4Bit Synchronous DRAM 4 Banks x 4M x 4Bit Synchronous DRAM 4 Banks x 4M x 4Bit Synchronous DRAM 4 Banks x 4M x 4Bit Synchronous DRAM
Maker - SK Hynix SK Hynix SK Hynix SK Hynix SK Hynix
Parts packaging code - TSOP2 TSOP2 TSOP2 TSOP2 TSOP2
package instruction - TSOP2, TSOP54,.46,32 TSOP2, TSOP54,.46,32 TSOP2, TSOP54,.46,32 TSOP2, TSOP54,.46,32 TSOP2, TSOP54,.46,32
Contacts - 54 54 54 54 54
Reach Compliance Code - unknow unknow unknow unknow unknow
ECCN code - EAR99 EAR99 EAR99 EAR99 EAR99
access mode - FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST
Maximum access time - 5.4 ns 6 ns 6 ns 5.4 ns 5.4 ns
Other features - AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH
Maximum clock frequency (fCLK) - 133 MHz 100 MHz 100 MHz 133 MHz 133 MHz
I/O type - COMMON COMMON COMMON COMMON COMMON
interleaved burst length - 1,2,4,8 1,2,4,8 1,2,4,8 1,2,4,8 1,2,4,8
JESD-30 code - R-PDSO-G54 R-PDSO-G54 R-PDSO-G54 R-PDSO-G54 R-PDSO-G54
JESD-609 code - e6 e6 e6 e6 e6
length - 22.238 mm 22.238 mm 22.238 mm 22.238 mm 22.238 mm
memory density - 67108864 bi 67108864 bi 67108864 bi 67108864 bi 67108864 bi
Memory IC Type - SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM
memory width - 4 4 4 4 4
Number of functions - 1 1 1 1 1
Number of ports - 1 1 1 1 1
Number of terminals - 54 54 54 54 54
word count - 16777216 words 16777216 words 16777216 words 16777216 words 16777216 words
character code - 16000000 16000000 16000000 16000000 16000000
Operating mode - SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
Maximum operating temperature - 70 °C 70 °C 70 °C 70 °C 70 °C
organize - 16MX4 16MX4 16MX4 16MX4 16MX4
Output characteristics - 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
Package body material - PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code - TSOP2 TSOP2 TSOP2 TSOP2 TSOP2
Encapsulate equivalent code - TSOP54,.46,32 TSOP54,.46,32 TSOP54,.46,32 TSOP54,.46,32 TSOP54,.46,32
Package shape - RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form - SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE
power supply - 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
Certification status - Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
refresh cycle - 4096 4096 4096 4096 4096
Maximum seat height - 1.194 mm 1.194 mm 1.194 mm 1.194 mm 1.194 mm
self refresh - YES YES YES YES YES
Continuous burst length - 1,2,4,8,FP 1,2,4,8,FP 1,2,4,8,FP 1,2,4,8,FP 1,2,4,8,FP
Maximum standby current - 0.002 A 0.002 A 0.002 A 0.002 A 0.002 A
Maximum slew rate - 0.16 mA 0.16 mA 0.16 mA 0.16 mA 0.16 mA
Maximum supply voltage (Vsup) - 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V
Minimum supply voltage (Vsup) - 3 V 3 V 3 V 3 V 3 V
Nominal supply voltage (Vsup) - 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
surface mount - YES YES YES YES YES
technology - CMOS CMOS CMOS CMOS CMOS
Temperature level - COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
Terminal surface - TIN BISMUTH TIN BISMUTH TIN BISMUTH TIN BISMUTH TIN BISMUTH
Terminal form - GULL WING GULL WING GULL WING GULL WING GULL WING
Terminal pitch - 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm
Terminal location - DUAL DUAL DUAL DUAL DUAL
width - 10.16 mm 10.16 mm 10.16 mm 10.16 mm 10.16 mm
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