dsPIC33EVXXXGM00X/10X FAMILY
16-Bit, 5V Digital Signal Controllers with
PWM, SENT, Op Amps and Advanced Analog Features
Operating Conditions
• 4.5V to 5.5V, -40°C to +85°C, DC to 70 MIPS
• 4.5V to 5.5V, -40°C to +125°C, DC to 60 MIPS
• 4.5V to 5.5V, -40°C to +150°C, DC to 40 MIPS
PWM
• Up to Six Pulse-Width Modulation (PWM) Outputs
(three generators)
• Primary Master Time Base Inputs allow
Time Base Synchronization from Internal/External
Sources
• Dead Time for Rising and Falling Edges
• 7.14 ns PWM Resolution
• PWM Support for:
- DC/DC, AC/DC, inverters, Power Factor
Correction (PFC) and lighting
- Brushless Direct Current (BLDC), Permanent
Magnet Synchronous Motor (PMSM),
AC Induction Motor (ACIM), Switched
Reluctance Motor (SRM)
- Programmable Fault inputs
- Flexible trigger configurations for
Analog-to-Digital conversion
- Supports PWM lock, PWM output chopping
and dynamic phase shifting
Core: 16-Bit dsPIC33E CPU
•
•
•
•
•
•
•
Code-Efficient (C and Assembly) Architecture
16-Bit Wide Data Path
Two 40-Bit Wide Accumulators
Single-Cycle (MAC/MPY) with Dual Data Fetch
Single-Cycle, Mixed-Sign MUL plus Hardware
Divide
32-Bit Multiply Support
Intermediate Security for Memory:
- Provides a Boot Flash Segment in addition to
the existing General Flash Segment
Error Code Correction (ECC) for Flash
Added Two Alternate Register Sets for Fast
Context Switching
•
•
Clock Management
Internal, 15% Low-Power RC (LPRC) – 32 kHz
Internal, 1% Fast RC (FRC) – 7.37 MHz
Internal, 10% Backup FRC (BFRC) – 7.37 MHz
Programmable PLLs and Oscillator Clock Sources
Fail-Safe Clock Monitor (FSCM)
Additional FSCM Source (BFRC), Intended to
Provide a Clock Fail Switch Source for the
System Clock
• Independent Watchdog Timer (WDT)
• System Windowed Watchdog Timer (DMT)
• Fast Wake-up and Start-up
•
•
•
•
•
•
Advanced Analog Features
• ADC module:
- Configurable as 10-bit, 1.1 Msps with
four S&H or 12-bit, 500 ksps with one S&H
- Up to 36 analog inputs
• Flexible and Independent ADC Trigger Sources
• Up to Four Op Amp/Comparators with Direct
Connection to the ADC module:
- Additional dedicated comparator and
7-bit Digital-to-Analog Converter (DAC)
- Two comparator voltage reference outputs
- Programmable references with 128 voltage
points
- Programmable blanking and filtering
• Charge Time Measurement Unit (CTMU):
- Supports mTouch
®
capacitive touch sensing
- Provides high-resolution time
measurement (1 ns)
- On-chip temperature measurement
- Temperature sensor diode
- Nine sources of edge input triggers (CTED1,
CTED2, OCPWM, TMR1, SYSCLK, OSCLK,
FRC, BFRC and LPRC)
Power Management
• Low-Power Management modes (Sleep, Idle
and Doze)
• Power Consumption Minimized Executing
NOP
String
• Integrated Power-on Reset (POR) and Brown-out
Reset (BOR)
• 0.5 mA/MHz Dynamic Current (typical)
• 50 µA at +25°C I
PD
Current (typical)
2013-2016 Microchip Technology Inc.
DS70005144E-page 1
dsPIC33EVXXXGM00X/10X FAMILY
Timers/Output Compare/Input Capture
• Nine General Purpose Timers:
- Five 16-bit and up to two 32-bit
timers/counters; Timer3 can provide ADC
trigger
• Four Output Compare modules Configurable as
Timers/Counters
• Four Input Capture modules
Input/Output
• GPIO Registers to Support Selectable
Slew Rate I/Os
• Peripheral Pin Select (PPS) to allow Function
Remap
• Sink/Source: 8 mA or 12 mA, Pin-Specific for
Standard V
OH
/V
OL
• Selectable Open-Drain, Pull-ups and Pull-Downs
• Change Notice Interrupts on All I/O Pins
Communication Interfaces
• Two Enhanced Addressable Universal
Asynchronous Receiver/Transmitter (UART)
modules (6.25 Mbps):
- With support for LIN/J2602 bus and IrDA
®
- High and low speed (SCI)
• Two SPI modules (15 Mbps):
- 25 Mbps data rate without using PPS
• One I
2
C module (up to 1 Mbaud) with SMBus
Support
• Two SENT J2716 (Single-Edge Nibble
Transmission-Transmit/Receive) module for
Automotive Applications
• One CAN module:
- 32 buffers, 16 filters and three masks
Qualification and Class B Support
• AEC-Q100 REVG (Grade 1: -40°C to +125°C)
Compliant
• AEC-Q100 REVG (Grade 0: -40°C to +150°C)
Compliant
• Class B Safety Library, IEC 60730
Class B Fault Handling Support
• Backup FRC
• Windowed WDT uses LPRC
• Windowed Deadman Timer (DMT) uses System
Clock (System Windowed Watchdog Timer)
• H/W Clock Monitor Circuit
• Oscillator Frequency Monitoring through CTMU
(OSCI, SYSCLK, FRC, BFRC, LPRC)
• Dedicated PWM Fault Pin
• Lockable Clock Configuration
Direct Memory Access (DMA)
• 4-Channel DMA with User-Selectable Priority
Arbitration
• UART, Serial Peripheral Interface (SPI), ADC,
Input Capture, Output Compare and Controller
Area Network (CAN)
Debugger Development Support
• In-Circuit and In-Application Programming
• Three Complex and Five Simple Breakpoints
• Trace and Run-Time Watch
DS70005144E-page 2
2013-2016 Microchip Technology Inc.
dsPIC33EVXXXGM00X/10X PRODUCT FAMILIES
The device names, pin counts, memory sizes and peripheral availability of each device are listed in
Table 1.
The following pages show the devices’ pinout diagrams.
General Purpose I/O (GPIO)
Peripheral Pin Select (PPS)
Program Memory Bytes
2013-2016 Microchip Technology Inc.
DS70005144E-page 3
TABLE 1:
dsPIC33EVXXXGM00X/10X FAMILY DEVICES
Op Amp/Comparators
External Interrupts
16-Bit Timers (T1)
Output Compare
DMA Channels
10/12-Bit ADC
Input Capture
32-Bit Timers
SRAM Bytes
ADC Inputs
Device
dsPIC33EV32GM002
dsPIC33EV32GM102
dsPIC33EV64GM002
dsPIC33EV64GM102
dsPIC33EV128GM002
dsPIC33EV128GM102
dsPIC33EV256GM002
dsPIC33EV256GM102
dsPIC33EV32GM004
dsPIC33EV32GM104
dsPIC33EV64GM004
dsPIC33EV64GM104
dsPIC33EV128GM004
dsPIC33EV128GM104
dsPIC33EV256GM004
dsPIC33EV256GM104
dsPIC33EV32GM006
dsPIC33EV32GM106
dsPIC33EV64GM006
dsPIC33EV64GM106
dsPIC33EV128GM006
dsPIC33EV128GM106
dsPIC33EV256GM006
dsPIC33EV256GM106
32K
4K
0
Packages
Security
CTMU
UART
SENT
PWM
CAN
Pins
SPI
I
2
C
dsPIC33EVXXXGM00X/10X FAMILY
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
4
5
2
4
4
3x2
2
2
1
2
1
36
4/5
1
Intermediate
Y
53
3
64
TQFP, QFN
4
5
2
4
4
3x2
2
2
1
2
1
24
4/5
1
Intermediate
Y
35
3
44
TQFP, QFN
4
5
2
4
4
3x2
2
2
1
2
1
11
3/4
1
Intermediate
Y
21
3
28
SPDIP, SOIC,
SSOP, QFN-S
64K
128K
256K
32K
64K
128K
256K
32K
64K
128K
256K
8K
8K
16K
4K
8K
8K
16K
4K
8K
8K
16K
dsPIC33EVXXXGM00X/10X FAMILY
Pin Diagrams
28-Pin SPDIP/SOIC/SSOP
(1,2,3)
MCLR
OA2OUT/AN0/C2IN4-/C4IN3-/RPI16/RA0
OA2IN+/AN1/C2IN1+/RPI17/RA1
PGED3/OA2IN-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
PGEC3/OA1OUT/AN3/C1IN4-/C4IN2-/RPI33/CTED1/RB1
PGEC1/OA1IN+/AN4/C1IN3-/C1IN1+/C2IN3-/RPI34/RB2
PGED1/OA1IN-/AN5/C1IN1-/CTMUC/RP35/RB3
V
SS
OSC1/CLKI/AN32/RPI18/RA2
OSC2/CLKO/RPI19/RA3
FLT32/RP36/RB4
OA5IN+/AN24/C5IN3-/C5IN1+/RP20/T1CK/RA4
V
DD
PGED2/SDA1/RP37/RB5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AV
DD
AV
SS
RPI47/PWM1L1/T5CK/RB15
RPI46/PWM1H1/T3CK/RB14
RPI45/PWM1L2/CTPLS/RB13
RPI44/PWM1H2/RB12
RP43/PWM1L3/RB11
RP42/PWM1H3/RB10
V
CAP
V
SS
OA5IN-/AN27/C5IN1-/ASDA1/SDI1/RP41/RB9
AN26/CV
REF1O
/ASCL1/SDO1/RP40/T4CK/RB8
OA5OUT/AN25/C5IN4-/C4IN1+/SCK1/RP39/INT0/RB7
PGEC2/SCL1/RP38/RB6
Note 1:
The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See
Section 11.5 “Peripheral
Pin Select (PPS)”
for available peripherals and information on limitations.
2:
Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See
Section 11.0 “I/O
Ports”
for more information.
3:
If the op amp is selected when OPAEN (CMxCON<10>) =
1,
the OAx input is used; otherwise, the ANx input is
used.
dsPIC33EV32GM002/102
dsPIC33EV64GM002/102
dsPIC33EV128GM002/102
dsPIC33EV256GM002/102
DS70005144E-page 4
2013-2016 Microchip Technology Inc.
dsPIC33EVXXXGM00X/10X FAMILY
Pin Diagrams (Continued)
28-Pin QFN-S
(1,2,3,4)
OA2OUT/AN0/C2IN4-/C4IN3-/RPI16/RA0
OA2IN+/AN1/C2IN1+/RPI17/RA1
28 27 26 25 24 23 22
PGED3/OA2IN-/AN2/C21N1-/SS1/RPI32/CTED2/RB0
PGEC3/OA1OUT/AN3/C1IN4-/C4IN2-/RPI33/CTED1/RB1
PGEC1/OA1IN+/AN4/C1IN3-/C1IN1+/C2IN3-/RPI34/RB2
PGED1/OA1IN-/AN5/C1IN1-/CTMUC/RP35/RB3
V
SS
OSC1/CLKI/AN32/RPI18/RA2
OSC2/CLKO/RPI19/RA3
1
2
3
21
20
RPI45/PWM1L2/CTPLS/RB13
RPI44/PWM1H2/RB12
RP43/PWM1L3/RB11
RP42/PWM1H3/RB10
V
CAP
V
SS
OA5IN-/AN27/C5IN1-/ASDA1/SDI1/RP41/RB9
dsPIC33EV 32GM002/102
19
dsPIC33EV 64GM002/102
4
dsPIC33EV 128GM002/102
18
5
dsPIC33EV256GM002/102
17
6
7
8
FLT32/RP36/RB4
9 10 11 12 13 14
OA 5 IN+/AN24/C5IN3-/C5 IN1+/RP20/T1CK/RA4
OA5OUT/AN25/C5IN4-/C4IN1+/SCK1/RP39/INT0/RB7
PGED2/SDA1/RP37/RB5
PGEC2/SCL1/RP38/RB6
V
DD
AN26/CV
REF1O
/ASCL1/SDO1/RP40/T4CK/RB8
16
15
Note 1:
The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See
Section 11.5 “Peripheral
Pin Select (PPS)”
for available peripherals and information on limitations.
2:
Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See
Section 11.0 “I/O
Ports”
for more information.
3:
If the op amp is selected when OPAEN (CMxCON<10>) =
1,
the OAx input is used; otherwise, the ANx input is
used.
4:
The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to
V
SS
externally.
2013-2016 Microchip Technology Inc.
RPI46/PWM1H1/T3CK/RB14
RPI47/PWM1L1/T5CK/RB15
MCLR
AV
DD
AV
SS
DS70005144E-page 5
京公网安备 11010802033920号
EEWORLD
