Crystal-to-HCSL, 100MHz PCI Express
™
Clock Synthesizer
841S101
Datasheet
General Description
The 841S101 is a PLL-based clock synthesizer specifically designed
for PCI_Express™ Clock applications. This device generates a
100MHz differential HCSL clock from a input reference of 25MHz.
The input reference may be derived from an external source or by the
addition of a 25MHz crystal to the on-chip crystal oscillator. An
external reference is applied to the XTAL_IN pin with the XTAL_OUT
pin left floating.The device offers spread spectrum clock output for
reduced EMI applications. An I
2
C bus interface is used to enable or
disable spread spectrum operation as well as select either a down
spread value of -0.35% or -.5%.The 841S101 is available in a
lead-free 16-Lead TSSOP package.
Features
•
•
•
•
•
•
•
•
•
•
•
One 0.7V current mode differential HCSL output pair
Crystal oscillator interface: 25MHz
Output frequency: 100MHz
RMS phase jitter @ 100MHz (12kHz – 20MHz): 1.23ps (typical)
Cycle-to-cycle jitter: 20ps (maximum)
I
2
C support with readback capabilities up to 400kHz
Spread Spectrum for electromagnetic interference (EMI) reduction
3.3V operating supply mode
-40°C to 85°C ambient operating temperature
Available in a lead-free (RoHS 6) package
PCI Express Gen 1, 2 and 3 jitter compliant
HiPerClockS™
Block Diagram
XTAL_IN
XTAL_OUT
SDATA
SCLK
IREF
Pullup
Pullup
25MHz
Pin Assignment
V
SS
OSC
PLL
Divider
Network
SRCT0
SRCC0
V
DD
1
2
3
4
5
6
7
8
I
2
C
Logic
SRCT0
SRCC0
V
D D
V
SS
IREF
V
SS
16
15
14
13
12
11
10
9
V
D D
SDATA
SCLK
XTAL_ OUT
XTAL_IN
V
D D
V
SS
V
D DA
841S101
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Top View
©2016 Integrated Device Technology, Inc.
1
Revision B, May 25, 2016
841S101 Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1, 6, 8, 10
2, 5, 11, 16
3, 4
7
9
12, 13
14
15
Name
V
SS
V
DD
SRCT0, SRCC0
IREF
V
DDA
XTAL_IN,
XTAL_OUT
SCLK
SDATA
Type
Power
Power
Output
Input
Power
Input
Input
I/O
Pullup
Pullup
Description
Power supply ground.
Power supply pins.
Differential output pair. HCSL interface levels.
An external fixed precision resistor (475
) from this pin to ground provides a
reference current used for differential current-mode SRCCx, SRCTx clock
outputs.
Analog supply for PLL.
Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
I
2
C compatible SCLK. This pin has an internal pullup resistor. Open drain.
LVCMOS/LVTTL interface levels.
I
2
C compatible SDATA. This pin has an internal pullup resistor.
LVCMOS/LVTTL interface levels.
NOTE:
Pullup
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
Parameter
Input Capacitance
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
51
Maximum
Units
pF
k
©2016 Integrated Device Technology, Inc.
2
Revision B, May 25, 2016
841S101 Datasheet
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a
two-signal I
2
C serial interface is provided. Through the Serial Data
Interface, various device functions, such as clock output buffers, can
be individually enabled or disabled. The registers associated with the
serial interface initialize to their default setting upon power-up, and
therefore, use of this interface is optional. Clock device register
changes are normally made upon system initialization, if any are
required.
Data Protocol
The clock driver serial protocol accepts bye write, byte read, block
write and block read operations from the controller. For block
write/read operation, the bytes must be accessed is sequential order
from lowest to highest byte (most significant bit first) with the ability to
stop after any complete byte has been transferred. For byte write and
byte read operations, the system controller can access individually
indexed bytes. The offset of the indexed byte is encoded in the
command code, as described in Table 3A.
The block write and block read protocol is outlined in Table 3B, while
Table 3C outlines the corresponding byte write and byte read
protocol. The slave receiver address is 11010010 (D2h).
Table 3A.Command Code Definition
Bit
7
6:5
4:0
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation.
Chip select address, set to “00” to access device.
Byte offset for byte read or byte write operation. For block read or block write operations, these bits must be “00000”.
©2016 Integrated Device Technology, Inc.
3
Revision B, May 25, 2016
841S101 Datasheet
Table 3B. Block Read and Block Write Protocol
Bit
1
2:8
9
10
11:18
19
20:27
28
29:36
37
38:45
46
Description = Block Write
Start
Slave address - 7 bits
Write
Acknowledge from slave
Command Code - 8 bits
Acknowledge from slave
Byte Count - 8 bits
Acknowledge from slave
Data byte 1 - 8 bits
Acknowledge from slave
Data byte 2 - 8 bits
Acknowledge from slave
Data Byte/Slave Acknowledges
Data Byte N - 8 bits
Acknowledge from slave
Stop
Bit
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
39:46
47
48:55
56
Description = Block Read
Start
Slave address - 7 bits
Write
Acknowledge from slave
Command Code - 8 bits
Acknowledge from slave
Repeat start
Slave address - 7 bits
Read = 1
Acknowledge from slave
Byte Count from slave - 8 bits
Acknowledge
Data Byte 1 from slave - 8 bits
Acknowledge
Data Byte 2 from slave - 8 bits
Acknowledge
Data Bytes from Slave/Acknowledge
Data Byte N from slave - 8 bits
Not Acknowledge
Table 3C. Byte Read and Byte Write Protocol
Bit
1
2:8
9
10
11:18
19
20:27
28
29
Description = Byte Write
Start
Slave address - 7 bits
Write
Acknowledge from slave
Command Code - 8 bits
Acknowledge from slave
Data Byte - 8 bits
Acknowledge from slave
Stop
Bit
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
39
Description = Byte Read
Start
Slave address - 7 bits
Write
Acknowledge from slave
Command Code - 8 bits
Acknowledge from slave
Repeat start
Slave address - 7 bits
Read
Acknowledge from slave
Data from slave - 8 bits
Not Acknowledge
Stop
©2016 Integrated Device Technology, Inc.
4
Revision B, May 25, 2016
841S101 Datasheet
Control Registers
Table 3D. Byte 0: Control Register 0
Bit
7
6
5
4
3
2
1
0
@Pup
0
1
1
1
1
1
0
0
Name
Reserved
Reserved
Reserved
Reserved
Reserved
SRC[T/C]0
Reserved
Reserved
Description
Reserved
Reserved
Reserved
Reserved
Reserved
SRC[T/C]0 Output Enable
0 = Disable (Hi-Z)
1 = Enable
Reserved
Reserved
Table 3G. Byte 3:Control Register 3
Bit
7
6
5
4
3
2
1
0
@Pup
1
0
1
0
1
1
1
1
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
NOTE: Pup denotes Power-up.
Table 3E. Byte 1: Control Register 1
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 3H. Byte 4: Control Register 4
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
1
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 3F. Byte 2: Control Register 2
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
0
1
0
1
1
Name
SRCT/C
Reserved
Reserved
Reserved
Reserved
SRC
Reserved
Reserved
Description
Spread Spectrum Selection
0 = -0.35%, 1 = - 0.5%
Reserved
Reserved
Reserved
Reserved
SRC Spread Spectrum Enable
0 = Spread Off,
1 = Spread On
Reserved
Reserved
Table 3I. Byte 5: Control Register 5
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
©2016 Integrated Device Technology, Inc.
5
Revision B, May 25, 2016
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