AD558–SPECIFICATIONS
(@ T = +25 C, V
A
CC
= +5 V to +15 V unless otherwise noted)
AD558S
1
Min
Typ
AD558T
1
Typ
Model
Min
RESOLUTION
RELATIVE ACCURACY
2
0°C to +70°C
–55°C to +125°C
OUTPUT
Ranges
3
Current Source
Sink
OUTPUT SETTLING TIME
5
0 to 2.56 Volt Range
0 to 10 Volt Range
4
FULL-SCALE ACCURACY
6
@ 25°C
T
MIN
to T
MAX
ZERO ERROR
@ 25°C
T
MIN
to T
MAX
MONOTONICITY
7
T
MIN
to T
MAX
DIGITAL INPUTS
T
MIN
to T
MAX
Input Current
Data Inputs, Voltage
Bit On-Logic “1”
Bit On-Logic “0”
Control Inputs, Voltage
On-Logic “1”
On-Logic “0”
Input Capacitance
TIMING
8
t
W
, Strobe Pulse Width
T
MIN
to T
MAX
t
DH
Data Hold Time
T
MIN
to T
MAX
t
DS
Data Set-Up Time
T
MIN
to T
MAX
POWER SUPPLY
Operating Voltage Range (V
CC
)
2.56 Volt Range
10 Volt Range
Current (I
CC
)
Rejection Ratio
POWER DISSIPATION, V
CC
= 5 V
V
CC
= 15 V
OPERATING TEMPERATURE RANGE 0
+5
AD558J
Typ
Max
8
±
1/2
Min
AD558K
Typ
Max
8
±
1/4
Max
8
±
1/2
±
3/4
Min
Max
8
±
1/4
±
3/8
Units
Bits
LSB
LSB
V
V
mA
0 to +2.56
0 to +10
+5
Internal Passive
Pull-Down to Ground
4
0.8
2.0
1.5
3.0
1.5
2.5
1
2
Guaranteed
0 to +2.56
0 to +10
+5
Internal Passive
Pull-Down to Ground
0.8
2.0
1.5
3.0
0.5
1
1/2
1
Guaranteed
0 to +2.56
0 to +10
+5
Internal Passive
Pull-Down to Ground
0.8
2.0
1.5
3.0
1.5
2.5
1
2
Guaranteed
0 to +2.56
0 to +10
Internal Passive
Pull-Down to Ground
0.8
2.0
1.5
3.0
0.5
1
1/2
1
Guaranteed
µs
µs
LSB
LSB
LSB
LSB
±
100
2.0
0
2.0
0
4
200
270
10
10
200
270
200
270
10
10
200
270
2.0
0
2.0
0
4
±
100
2.0
0
2.0
0
4
200
270
10
10
200
270
±
100
2.0
0
2.0
0
4
200
270
10
10
200
270
100
µA
V
V
V
V
pF
ns
ns
ns
ns
ns
ns
0.8
0.8
0.8
0.8
0.8
+4.5
+11.4
15
75
225
+16.5
+16.5
25
0.03
125
375
+70
+4.5
+11.4
15
75
225
0
+16.5
+16.5
25
0.03
125
375
+70
+4.5
+11.4
15
75
225
–55
+16.5
+16.5
25
0.03
125
375
+125
+4.5
+11.4
15
75
225
–55
+16.5
+16.5
25
0.03
125
375
+125
V
V
mA
%/%
mW
mW
°C
NOTES
1
The AD558 S & T grades are available processed and screened lo MIL-STD-883 Class B. Consult Analog Devices’ Military Databook for details.
2
Relative Accuracy is defined as the deviation of the code transition points from the ideal transfer point on a straight line from the offset to the full scale of the device.
See “Measuring Offset Error”.
3
Operation of the 0 volt to 10 volt output range requires a minimum supply voltage of +11.4 volts.
4
Passive pull-down resistance is 2 kΩ for 2.56 volt range, 10 kΩ for 10 volt range.
5
Settling time is specified for a positive-going full-scale step to
±
1/2 LSB. Negative-going steps to zero are slower, but can be improved with an external pull-down.
6
The full range output voltage for the 2.56 range is 2.55 V and is guaranteed with a +5 V supply, for the 10 V range, it is 9.960 V guaranteed with a +15 V supply.
7
A monotonic converter has a maximum differential linearity error of
±
1 LSB.
8
See Figure 7.
Specifications shown in
boldface
are tested on all production units at final electrical test.
Specifications subject to change without notice.
–2–
REV.
B
AD558
ABSOLUTE MAXIMUM RATINGS*
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
DB1
3
2
1 20 19
V
OUT
SENSE
DB0 (LSB)
NC
V
OUT
V
CC
to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +18 V
Digital Inputs (Pins 1–10) . . . . . . . . . . . . . . . . . . 0 V to +7.0 V
V
OUT
. . . . . . . . . . . . . . . . . . . . . . . Indefinite Short to Ground
Momentary Short to V
CC
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW
Storage Temperature Range
N/P (Plastic) Packages . . . . . . . . . . . . . . . . –25°C to +100°C
D (Ceramic) Package . . . . . . . . . . . . . . . . . –55°C to +150°C
Lead Temperature (soldering, 10 sec) . . . . . . . . . . . . . +300°C
Thermal Resistance
Junction to Ambient/Junction to Case
D (Ceramic) Package . . . . . . . . . . . . . . 100°C/W/30°C/W
N/P (Plastic) Packages . . . . . . . . . . . . . 140°C/W/55°C/W
(LSB) DB0
1
16 V
OUT
15 V
OUT
SENSE
14 V
OUT
SELECT
DB1 2
DB2 3
DB3 4
DB4 5
DB5 6
DB6
7
AD558
13 GND
TOP VIEW
12 GND
(Not to Scale)
11 +V
CC
10 CS
9
CE
(MSB) DB7 8
Figure 1a. AD558 Pin Configuration (DIP)
DB2 4
DB3 5
NC 6
DB4
DB5
7
8
18 V
OUT
SELECT
AD558
TOP VIEW
(Not to Scale)
17 GND
16 NC
15 GND
14 +V
CC
AD558 METALIZATION PHOTOGRAPH
Dimensions shown in inches and (mm).
9 10 11 12 13
(MSB) DB7
DB6
NC
CE
CS
NC = NO CONNECT
Figure 1b. AD558 Pin Configuration (PLCC and LCC)
Bond Pad Coordinates
Pad No.
1
2
3
4
5
6
7
8
9
10
11
12
2
13
3
14
15
16
Pad Name
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
CE
CS
V
CC
GND
GND
V
OUT
SELECT
V
OUT
SENSE
V
OUT
X Coordinate
−702
−927
−957
−957
−957
−957
−927
−702
47
272
957
957
946
923
689
−461
Y Coordinate
1265
1265
1004
347
115
−111
−1248
−1248
−1248
−1248
−1225
−965
970
1265
1265
1265
REV.
B
–3–
AD558
CIRCUIT DESCRIPTION
CHIP AVAILABILITY
The AD558 consists of four major functional blocks, fabricated
on a single monolithic chip (see Figure 2). The main D-to-A
converter section uses eight equally-weighted laser-trimmed
current sources switched into a silicon-chromium thin-film
R/2R resistor ladder network to give a direct but unbuffered 0
mV to 400 mV output range. The transistors that form the
DAC switches are PNPs; this allows direct positive-voltage logic
interface and a zero-based output range.
DIGITAL INPUT DATA
CONTROL
INPUTS
LSB
MSB
The AD558 is available in laser-trimmed, passivated chip form.
AD558J and AD558T chips are available. Consult the factory
for details.
Input Logic Coding
Digital Input Code
Binary
0000 0000
0000 0001
0000 0010
0000 1111
0001 0000
0111 1111
1000 0000
1100 0000
1111 1111
Hexadecimal Decimal
00
01
02
0F
10
7F
80
C0
FF
0
1
2
15
16
127
128
192
255
Output Voltage
2.56 V Range 10.000 V Range
0
0.010 V
0.020 V
0.150 V
0.160 V
1.270 V
1.280 V
1.920 V
2.55 V
0
0.039 V
0.078 V
0.586 V
0.625 V
4.961 V
5.000 V
7.500 V
9.961 V
DB0
DB1
DB2
DB4
DB3
CS
CE
DB5
DB6
DB7
+V
CC
GND
GND
I
2
L
CONTROL
LOGIC
BAND-
GAP
REFERENCE
CONTROL
AMP
I
2
L LATCHES
8-BIT VOLTAGE-SWITCHING
D-TO-A CONVERTER
OUTPUT
AMP
V
OUT
V
OUT
SENSE
V
OUT
SELECT
CONNECTING THE AD558
Figure 2. AD558 Functional Block Diagram
The high speed output buffer amplifier is operated in the non-
inverting mode with gain determined by the user-connections
at the output range select pin. The gain-setting application
resistors are thin-film laser-trimmed to match and track the
DAC resistors and to assure precise initial calibration of the two
output ranges, 0 V to 2.56 V and 0 V to 10 V. The amplifier
output stage is an NPN transistor with passive pull-down for
zero-based output capability with a single power supply. The
internal precision voltage reference is of the patented bandgap
type. This design produces a reference voltage of 1.2 volts and
thus, unlike 6.3 volt temperature compensated Zeners, may be
operated from a single, low voltage logic power supply. The
microprocessor interface logic consists of an 8-bit data latch and
control circuitry. Low power, small geometry and high speed
are advantages of the I
2
L design as applied to this section. I
2
L is
bipolar process compatible so that the performance of the ana-
log sections need not be compromised to provide on-chip logic
capabilities. The control logic allows the latches to be operated
from a decoded microprocessor address and write signal. If the
application does not involve a
µP
or data bus, wiring CS and
CE to ground renders the latches “transparent” for direct DAC
access.
MIL-STD-883
The AD558 has been configured for ease of application. All ref-
erence, output amplifier and logic connections are made inter-
nally. In addition, all calibration trims are performed at the
factory assuring specified accuracy without user trims. The only
connection decision that must be made by the user is a single
jumper to select output voltage range. Clean circuit board lay-
out is facilitated by isolating all digital bit inputs on one side of
the package; analog outputs are on the opposite side.
Figure 3 shows the two alternative output range connections.
The 0 V to 2.56 V range may be selected for use with any power
supply between +4.5 V and +16.5 V. The 0 V to 10 V range
requires a power supply of +11.4 V to +16.5 V.
OUTPUT
AMP
16
15
14
13
V
OUT
V
OUT
SENSE
V
OUT
SELECT
GND
OUTPUT
AMP
16
15
14
13
V
OUT
V
OUT
SENSE
V
OUT
SELECT
GND
a. 0 V to 2.56 V Output Range b. 0 V to 10 V Output Range
Figure 3. Connection Diagrams
The rigors of the military/aerospace environment, temperature
extremes, humidity, mechanical stress, etc., demand the utmost
in electronic circuits. The AD558, with the inherent reliability
of integrated circuit construction, was designed with these ap-
plications in mind. The hermetically-sealed, low profile DIP
package takes up a fraction of the space required by equivalent
modular designs and protects the chip from hazardous environ-
ments. To further ensure reliability, military temperature range
AD558 grades S and T are available screened to MIL-STD-883.
For more complete data sheet information consult the Analog
Devices’ Military Databook.
Because of its precise factory calibration, the AD558 is intended
to be operated without user trims for gain and offset; therefore
no provisions have been made for such user trims. If a small in-
crease in scale is required, however, it may be accomplished
by slightly altering the effective gain of the output buffer. A
resistor in series with V
OUT
SENSE will increase the output
range.
For example if a 0 V to 10.24 V output range is desired (40 mV
= 1 LSB), a nominal resistance of 850
Ω
is required. It must be
remembered that, although the internal resistors all ratio-
match and track, the
absolute
tolerance of these resistors is
typically
±
20% and the
absolute
TC is typically –50 ppm/°C
(0 to –100 ppm/°C). That must be considered when rescaling is
performed. Figure 4 shows the recommended circuitry for a
full-scale output range of 10.24 volts. Internal resistance values
shown are nominal.
–4–
REV.
B
Power technology
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