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PSB2115: DescriptionISDN PC Adapter Circuit IPAC; File Size3MB，317 Pages; ManufacturerSIEMENS; Websitehttp://www.infineon.com/

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ISDN PC Adapter Circuit IPAC

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PSB 2115 Version 1.1

Data Sheet 11.97

DS 1

PSB 2115

Revision History:

Current Version: 11.97

Previous Version: Preliminary Data Sheet 03.97

Page

(in previous (in new

Version)

Subjects (major changes since last revision)

For questions on technology, delivery and prices please contact the Semiconductor

Group Offices in Germany or the Siemens Companies and Representatives worldwide:

see our webpage at http://www.siemens.de/Semiconductor/address/address.htm.

Edition 11.97

Published by Siemens AG,

HL TS,

Balanstraße 73,

81541 München

Siemens AG 1997.

Attention please!

As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for

applications, processes and circuits implemented within components or assemblies.

The information describes the type of component and shall not be considered as assured characteristics.

Terms of delivery and rights to change design reserved.

Due to technical requirements components may contain dangerous substances. For information on the types in

question please contact your nearest Siemens Office, Semiconductor Group.

Siemens AG is an approved CECC manufacturer.

Packing

Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales

office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport.

For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice

you for any costs incurred.

Components used in life-support devices or systems must be expressly authorized for such purpose!

Critical components

of the Semiconductor Group of Siemens AG, may only be used in life-support devices or

systems

with the express written approval of the Semiconductor Group of Siemens AG.

1 A critical component is a component used in a life-support device or system whose failure can reasonably be

expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that

device or system.

2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or

maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be en-

dangered.

PSB 2115

PSF 2115

Table of Contents

1.1

1.2

1.3

1.4

1.5

1.6

2.1

2.1.1

2.1.2

2.1.3

2.1.4

2.1.5

2.1.6

2.1.7

2.1.7.1

2.1.7.2

2.1.8

2.1.9

2.1.10

2.1.11

2.1.12

2.2

2.2.1

2.2.1.1

2.2.1.2

2.2.1.3

2.3

2.3.1

2.3.2

2.3.3

2.3.4

2.3.4.1

2.3.4.2

2.3.4.3

2.3.4.4

2.3.4.5

2.3.5

Page

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

B-Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Non-Auto Mode (MODEB: MDS1, MDS0 = 01) . . . . . . . . . . . . . . . . . . . . . . .32

Transparent Mode 1 (MODEB: MDS1, MDS0, ADM = 101) . . . . . . . . . . . . .33

Transparent Mode 0 (MODEB: MDS1, MDS0, ADM = 100) . . . . . . . . . . . . .33

Extended Transparent Modes 0, 1 (MODEB: MDS1, MDS0 = 11) . . . . . . . .33

Receive Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Transmit Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Clock Mode 5 (Time-Slots) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Fully Transparent Transmission and Reception . . . . . . . . . . . . . . . . . . . . . . .39

Cyclic Transmission (Fully Transparent) . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Continuous Transmission (DMA Mode only) . . . . . . . . . . . . . . . . . . . . . . . . .40

Receive Length Check Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Data Inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

D-Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Layer-2 Functions for HDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Message Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Reception of Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Transmission of Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Control Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Activation Initiated by Exchange (LT-S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Activation Initiated by Terminal (TE/LT-T) . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

D-Channel Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

TIC Bus D-Channel Control in TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

S-Bus Priority Mechanism for D-Channel . . . . . . . . . . . . . . . . . . . . . . . . . . .56

S-Bus D-channel Control in TEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

S-Bus D-Channel Control in LT-T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

D-Channel Control in the Intelligent NT (TIC- and S-Bus) . . . . . . . . . . . . . . .59

IOM-2 Interface Channel Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

11.97

Semiconductor Group

PSB 2115

PSF 2115

Table of Contents

2.4

2.4.1

2.4.2

2.4.3

2.4.4

2.4.4.1

2.4.4.2

2.4.4.3

2.4.4.4

2.4.4.5

2.5

2.5.1

2.5.2

2.5.2.1

2.5.2.2

2.5.3

2.5.3.1

2.5.3.2

2.5.4

2.5.5

2.5.6

2.5.7

2.5.8

2.5.9

2.5.9.1

2.5.9.2

2.6

2.6.1

2.6.2

2.6.3

2.6.4

2.6.5

2.6.6

2.6.7

2.6.8

2.7

2.7.1

2.7.2

2.7.3

Page

S/T Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

S/T-Interface Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

S/T-Interface Multiframing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

S/T Transceiver Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

MON-8 Commands (Internal Register Access) . . . . . . . . . . . . . . . . . . . . . . .72

MON-8 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

MON-8 Loop-Back Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

MON-8 IOM-2 Channel Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

MON-8 SM/CI Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Layer-1 Functions for the S/T Interface . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Analog Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

S/T Interface Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

S/T Interface Pre-Filter Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

External Protection Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Receiver Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Receiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Level Detection Power Down (TE mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

S/T Transmitter Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

Timing Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Activation/Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

Activation Indication via Pin ACL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

Terminal Specific Functions (TE mode only) . . . . . . . . . . . . . . . . . . . . . . . . .94

Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

B-Channel Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

D-Channel and S/T Interface Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

Data Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

Interrupt Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

DMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

FIFO Structure for B-Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

Timer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

IOM-2 Frame Structure / Timing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

IOM-2 Interface Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

Microprocessor Access to B and IC Channels . . . . . . . . . . . . . . . . . . . . . . .125

11.97

Semiconductor Group

PSB 2115

PSF 2115

Table of Contents

2.7.4

2.7.4.1

2.7.4.2

2.7.4.3

2.7.4.4

2.7.5

2.7.6

2.8

2.8.1

2.8.2

2.8.2.1

2.8.2.2

2.8.2.3

2.9

Page

MONITOR Channel Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

Handshake Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

Monitor Procedure Timeout (TOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136

MON-1, MON-2 Commands (S/Q Channel Access) . . . . . . . . . . . . . . . . . .137

MON-8 Commands (Register Access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138

C/I-Channel Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

TIC Bus Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141

Auxiliary Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

Mode Dependent Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146

PCM Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146

Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

Switching of Timeslots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152

Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154

3.1

3.2

3.3

3.3.1

3.3.2

3.3.3

3.4

3.4.1

3.4.2

3.5

3.5.1

3.5.2

3.6

3.6.1

3.6.2

3.6.3

3.6.3.1

Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155

RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158

Interrupt Structure and Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163

B-Channel Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165

D-Channel Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167

Auxiliary Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

B-Channel Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174

Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174

Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180

D-Channel Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183

HDLC Frame Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183

HDLC Frame Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

Control of Layer-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188

Activation/Deactivation of IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . .188

Activation/Deactivation of S/T Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

State Machine TE/LT-T Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193

TE/LT-T Modes State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194

11.97

Semiconductor Group

PSB2115 Related Products

	PSB2115	PSF2115
Description	ISDN PC Adapter Circuit IPAC	ISDN PC Adapter Circuit IPAC

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