EP3SE260F1517I3N datasheet, PDF

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EP3SE260F1517I3N: DescriptionFPGA - Field Programmable Gate Array FPGA - Stratix III 10200 LABs 976 IOs; CategoryProgrammable logic devices Programmable logic; File Size191KB，16 Pages; ManufacturerAltera (Intel); Environmental Compliance

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EP3SE260F1517I3N Overview

FPGA - Field Programmable Gate Array FPGA - Stratix III 10200 LABs 976 IOs

EP3SE260F1517I3N Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Altera (Intel)
Parts packaging code	BGA
package instruction	LEAD FREE, FBGA-1517
Contacts	1517
Reach Compliance Code	not_compliant
ECCN code	3A001.A.7.A
Other features	IT CAN ALSO OPERATE FROM 1.05 TO 1.15V SUPPLY
maximum clock frequency	717 MHz
JESD-30 code	S-PBGA-B1517
JESD-609 code	e1
length	40 mm
Humidity sensitivity level	4
Number of entries	976
Number of logical units	255000
Output times	976
Number of terminals	1517
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA1517,39X39,40
Package shape	SQUARE
Package form	GRID ARRAY
power supply	1.2/3.3 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	3.9 mm
Maximum supply voltage	0.94 V
Minimum supply voltage	0.86 V
Nominal supply voltage	0.9 V
surface mount	YES
technology	CMOS
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	40 mm

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1. Stratix III Device Family Overview

SIII51001-1.8

The Stratix

III family provides one of the most architecturally advanced,

high-performance, low-power FPGAs in the marketplace.

Stratix III FPGAs lower power consumption through Altera’s innovative

Programmable Power Technology, which provides the ability to turn on the

performance where needed and turn down the power consumption for blocks not in

use. Selectable Core Voltage and the latest in silicon process optimizations are also

employed to deliver the industry’s lowest power, high-performance FPGAs.

Specifically designed for ease of use and rapid system integration, the Stratix III

FPGA family offers two variants optimized to meet different application needs:

■

The Stratix III

family provides balanced logic, memory, and multiplier ratios for

mainstream applications.

The Stratix III

family is memory- and multiplier-rich for data-centric

applications.

■

Modular I/O banks with a common bank structure for vertical migration lend

efficiency and flexibility to the high-speed I/O. Package and die enhancements with

dynamic on-chip termination, output delay, and current strength control provide

best-in-class signal integrity.

Based on a 1.1-V, 65-nm all-layer copper SRAM process, the Stratix III family is a

programmable alternative to custom ASICs and programmable processors for

high-performance logic, digital signal processing (DSP), and embedded designs.

Stratix III devices include optional configuration bit stream security through volatile

or non-volatile 256-bit Advanced Encryption Standard (AES) encryption. Where

ultra-high reliability is required, Stratix III devices include automatic error detection

circuitry to detect data corruption by soft errors in the configuration random-access

memory (CRAM) and user memory cells.

Features Summary

Stratix III devices offer the following features:

■

48,000 to 338,000 equivalent logic elements (LEs) ( refer to

Table 1–1)

2,430 to 20,497 Kbits of enhanced TriMatrix memory consisting of three RAM

block sizes to implement true dual-port memory and FIFO buffers

High-speed DSP blocks provide dedicated implementation of 9×9, 12×12, 18×18,

and 36×36 multipliers (at up to 550 MHz), multiply-accumulate functions, and

finite impulse response (FIR) filters

I/O:GND:PWR ratio of 8:1:1 along with on-die and on-package decoupling for

robust signal integrity

Programmable Power Technology, which minimizes power while maximizing

device performance

■

Altera Corporation

Stratix III Device Handbook, Volume 1

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