AD7899: 5 V Single Supply 14-Bit 400 kSPS ADC Data
Sheet
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SOFTWARE AND SYSTEMS REQUIREMENTS
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REFERENCE MATERIALS
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AD7899–SPECIFICATIONS
Parameter
SAMPLE AND HOLD
–0.1 dB Full Power Bandwidth
–3 dB Full Power Bandwidth
Aperture Delay
Aperture Jitter
DYNAMIC PERFORMANCE
2
AD7899-1
Signal to (Noise + Distortion)
Ratio
3
@ 25 C
T
MIN
to T
MAX
Total Harmonic Distortion
3
Peak Harmonic or Spurious Noise
3
AD7899-2
Signal to (Noise + Distortion)
Ratio
3
@ 25 C
T
MIN
to T
MAX
Total Harmonic Distortion
3
Peak Harmonic or Spurious Noise
3
AD7899-3
Signal to (Noise + Distortion)
Ratio
3
@ 25 C
T
MIN
to T
MAX
Total Harmonic Distortion
3
Peak Harmonic or Spurious Noise
3
Intermodulation Distortion
3
2nd Order Terms
3rd Order Terms
DC ACCURACY
Resolution
Relative Accuracy (INL)
3
Differential Nonlinearity (DNL)
3
AD7899-1
Input Voltage Range
Input Current
Positive Gain Error
3
Negative Gain Error
3
Bipolar Zero Error
AD7899-2
Input Voltage Range
Input Current
Positive Gain Error
3
Offset Error
3
AD7899-3
Input Voltage Range
Input Current
Positive Gain Error
3
Negative Gain Error
3
Bipolar Zero Error
REFERENCE INPUT/OUTPUT
V
REF
IN Input Voltage Range
V
REF
IN Input Capacitance
4
V
REF
OUT Output Voltage
V
REF
OUT Error @ 25 C
V
REF
OUT Error T
MIN
to T
MAX
V
REF
OUT Temperature Coefficient
V
REF
OUT Output Impedance
A
Version
1
500
4.5
20
25
(V
DD
= 5 V 5%, AGND = DGND = 0 V, V
REF
= Internal. Clock = Internal, all specifications
T
MIN
to T
MAX
and valid for V
DRIVE
= 3 V 5% and 5 V 5% unless otherwise noted.)
B
Version
1
500
4.5
20
25
S
Version
1
500
4.5
20
25
Unit
kHz typ
MHz typ
ns max
ps typ
f
IN
= 100 kHz, f
S
= 400 kSPS
Test Conditions/Comments
78
78
–84
–86
78
78
–84
–86
78
77
–82
–85
dB min
dB min
dB max
dB max
78
77
–82
–82
dB min
dB min
dB max
dB max
78
77
–84
–86
–89
–89
14
±
2
±
1
±
5,
±
10
0.8, 0.8
±
10
±
10
±
12
0 to 2.5
0 to 5
0.4, 800
±
14
±
10
±
2.5
0.8
±
14
±
14
±
14
2.375/2.625
10
2.5
±
10
±
20
25
6
78
77
–84
–86
–89
–89
14
±
1.5
±
1
±
5,
±
10
0.8, 0.8
±
8
±
8
±
8
–89
–89
14
±
2
±
1
dB min
dB min
dB max
dB max
fa = 49 kHz, fb = 50 kHz
dB typ
dB typ
Bits
LSB max
LSB max
Volts
mA max
LSB max
LSB max
LSB max
Volts
µA
max
LSB max
LSB max
V
IN
= 2.5 V, V
IN
= 5 V
No Missing Codes Guaranteed
±
12
±
12
±
12
V
IN
= –5 V and –10 V Respectively
±
2.5
0.8
±
12
±
12
±
12
2.375/2.625
10
2.5
±
10
±
20
25
6
2.375/2.625
10
2.5
±
10
±
25
25
6
Volts
mA max
LSB max
LSB max
LSB max
V
MIN
/V
MAX
pF max
V nom
mV max
mV max
ppm/ C typ
kΩ typ
V
IN
= –2.5 V
2.5 V
±
5%
See Reference Section
–2–
REV. A
AD7899
Parameter
L
OGIC INPUTS
A
Version
1
V
DRIVE
/2 + 0.4
V
DRIVE
/2 – 0.4
±
10
10
V
DRIVE
– 0.4
0.4
B
Version
1
V
DRIVE
/2 + 0.4
V
DRIVE
/2 – 0.4
±
10
10
V
DRIVE
– 0.4
0.4
S
Version
1
V
DRIVE
/2 + 0.4
V
DRIVE
/2 – 0.4
±
10
10
V
DRIVE
– 0.4
0.4
Unit
V min
V max
µA
max
pF max
V min
V max
Test Conditions/Comments
V
DD
= 5 V
±
5%
V
DD
= 5 V
±
5%
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN4
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
DB13–DB0
High Impedance
Leakage Current
Capacitance
4
Output Coding
AD7899-1, AD7899-3
AD7899-2
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time
2, 3
Throughput Time
POWER REQUIREMENTS
V
DD
I
DD
Normal Mode
Standby Mode
Power Dissipation
Normal Mode
Standby Mode
I
SOURCE
= 400
µA
I
SINK
= 1.6 mA
±
10
10
±
10
10
±
10
10
µA
max
pF max
Two’s Complement
Straight (Natural) Binary
2.2
0.3
400
5
25
20
2.2
0.3
400
5
25
20
2.2
0.3
400
5
25
20
µs
max
µs
max
kSPS max
V nom
mA max
µA
max
Typically 16 mA
(5
µA
typ) Logic Inputs = 0 V or
V
DD
Typically 80 mW, V
DD
= 5 V
125
100
125
100
125
125
mW max
µW
max
NOTES
1
Temperature Ranges are as follows : A, B Versions: –40 C to +85 C. S Version: –55°C to +125°C.
2
Performance measured through full channel (SHA and ADC).
3
See Terminology.
4
Sample tested @ 25°C to ensure compliance.
Specifications subject to change without notice.
REV. A
–3–
AD7899
TIMING CHARACTERISTICS
1, 2
(V
to T
MAX
and valid for V
DRIVE
= 3 V
Parameter
t
CONV
t
ACQ
t
EOC
t
WAKE-UP
– External V
REF5
t
1
t
2
Read Operation
t
3
t
4
t
5
t
6 3
t
7 4
t
8
External Clock
t
9
t
10
t
11
DD
5% and 5 V
A, B and S
Versions
2.2
2.46
0.3
120
180
2
35
70
= 5 V 5%, AGND = DGND = 0 V, V
REF
= Internal, Clock = Internal; All specifications T
MIN
5% unless otherwise noted.)
Unit
µs
max
µs
max
µs
max
ns min
ns max
µs
max
ns min
ns min
Test Conditions/Comments
Conversion Time, Internal Clock
CLKIN = 6.5 MHz
Acquisition Time
EOC Pulsewidth
STBY
Rising Edge to
CONVST
Rising Edge
(See Standby Mode Operation)
CONVST
Pulsewidth
CONVST
Rising Edge to BUSY Rising Edge
CS
to
RD
Setup Time
CS
to
RD
Hold Time
Read Pulsewidth
Data Access Time after Falling Edge of
RD,
V
DRIVE
= 5 V
Data Access Time after Falling Edge of
RD,
V
DRIVE
= 3 V
Bus Relinquish Time after Rising Edge of
RD
BUSY Falling Edge to
RD
Delay
CLKIN to
CONVST
Rising Edge Setup Time
CLKIN to
CONVST
Rising Edge Hold Time
CONVST
Rising Edge to CLK Falling Edge
0
0
35
35
40
5
30
0
0
20
100
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns min
ns min
ns min
ns min
NOTES
1
Sample tested at 25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of V
DRIVE
) and timed from a voltage level of V
DRIVE
/2.
2
See Figures 5, 6, 7, and 8.
3
Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.0 V.
4
These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
5
Refer to the Standby Mode Operation section.
Specifications subject to change without notice.
1.6mA
TO
OUTPUT
PIN
1.6V
50pF
400 A
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
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