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5962-8671601EA

Description
Analog Switch ICs
Categorysemiconductor    Analog mixed-signal IC   
File Size141KB,13 Pages
ManufacturerIntersil ( Renesas )
Websitehttp://www.intersil.com/cda/home/
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Analog Switch ICs

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Parameter NameAttribute value
Product AttributeAttribute Value
ManufacturerIntersil ( Renesas )
Product CategoryAnalog Switch ICs
ConfigurationSPST
On Resistance - Max50 Ohms
On Time - Max50 ns
Off Time - Max50 ns
Operating Supply Voltage+/- 15 V
Minimum Operating Temperature- 55 C
Maximum Operating Temperature+ 125 C
Package / CaseCDIP
Height3.56 mm (Max)
Length21.34 mm (Max)
Supply TypeDual Supply
Width7.87 mm (Max)
Supply Current - Max10 mA
Maximum Dual Supply Voltage+/- 18 V
Pd - Power Dissipation750 mW
3.3 V 1:11 LVCMOS Zero Delay Clock
Generator
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016
MPC93R52
DATA SHEET
The MPC93R52 is a 3.3V compatible, 1:11 PLL based clock generator
targeted for high performance clock tree applications. With output frequencies up
to 240MHz and output skews lower than 200ps, the device meets the needs of
most demanding clock applications.
Features
Configurable 11 Outputs LVCMOS PLL Clock Generator
Fully Integrated PLL
Wide Range of Output Clock Frequency of 16.67MHz to 240MHz
Multiplication of the Input Reference Clock Frequency by 3, 2, 1, 3
2, 2
3,
1
3, and 1
2
3.3 V LVCMOS Compatible
Maximum Output Skew of 200ps
Supports Zero-Delay Applications
Designed for High-Performance Telecom, Networking and Computing
Applications
32-Lead LQFP Package
32-Lead Pb-free Package Available
Ambient Temperature Range – 0°C to +70°C
Pin and Function Compatible to the MPC952
For functional replacement part use 8T49N285
MPC93R52
LOW VOLTAGE
3.3 V LVCMOS 1:11
CLOCK GENERATOR
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
The MPC93R52 is a fully 3.3 V compatible PLL clock generator and clock driver. The device has the capability to generate
output clock signals of 16.67MHz to 240MHz from external clock sources. The internal PLL is optimized for its frequency range
and does not require external look filter components. One output of the MPC93R52 has to be connected to the PLL feedback
input FB_IN to close the external PLL feedback path. The output divider of this output setting determines the PLL frequency mul-
tiplication factor. This multiplication factor, F_RANGE and the reference clock frequency must be selected to situate the VCO in
its specified lock range. The frequency of the clock outputs can be configured individually for all three output banks by the FSELx
pins supporting systems with different but phase-aligned clock frequencies.
The PLL of the MPC93R52 minimizes the propagation delay and therefore supports zero-delay applications. All inputs and
outputs are LVCMOS compatible. The outputs are optimized to drive parallel terminated 50
transmission lines. Alternatively,
each output can drive up to two series terminated transmission lines giving the device an effective fanout of 22.
The device also supports output high-impedance disable and a PLL bypass mode for static system test and diagnosis. The
MPC93R52 is packaged in a 32-lead LQFP.
MPC93R52 REVISION 6 3/14/16
1
©2016 Integrated Device Technology, Inc.
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