NM27LV010 1,048,576-Bit (128k x 8) Low Voltage EPROM
Connection Diagrams
PLCC Pin Configuration
A12
A15
A16
XX/V
PP
V
CC
XX/PGM
XX
TSOP Pin Configuration
A11
A9
A8
A13
A14
NC
PGM
VCC
VPP
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8 8 x 20 MM
9
TSOP
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
O7
O6
O5
O4
O3
VSS
O2
O1
O0
A0
A1
A2
A3
DS011377-2
4
3
2
1 32 31 30
A7
A6
A5
A4
A3
A2
A1
A0
O0
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20
29
28
27
26
25
24
23
22
21
A14
A13
A8
A9
A11
OE
A10
CE
O7
O1
O2
GND
O3
O4
O5
O6
DS011377-6
Top View
Top View
Commercial Temperature Range
(0
°
C to +70
°
C) V
CC
= 3.3
±
0.3
Parameter/Order Number
NM27LV010 V, T 200
NM27LV010 V, T 250
Industrial Temperature Range
(-40
°
C to +85
°
C) V
CC
= 3.3
±
0.3
Parameter/Order Number
NM27LV010 VE, TE
NM27LV010 VE, TE
Package Types: NM27LV010 V, T
Access Time (ns)
200
250
Access Time (ns)
200
250
Pin Names
A0–A16
CE
OE
O0–O7
PGM
XX
V
PP
Addresses
Chip Enable
Output Enable
Outputs
Program
Don’t Care (During Read)
Programming Voltage
V = PLCC
T = TSOP
• All packages conform to the JEDEC standard.
• All versions are guaranteed to function for slower speeds.
• Consult the Fairchild Sales office on new released products
and packages.
• Consult the Fairchild representative for custom products for
your specific application.
2
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NM27LV010 1,048,576-Bit (128k x 8) Low Voltage EPROM
Absolute Maximum Ratings
(Note 1)
Storage Temperature
All Input Voltages except A9 with
Respect to Ground (Note 10)
V
PP
and A9 with Respect to Ground
V
CC
Supply Voltage with
Respect to Ground
ESD Protection
-65°C to +150°C
All Output Voltages with
Respect to Ground (Note 10)
V
CC
+ 1.0V
to GND - 0.6V
Operating Range
-0.6V to +7V
-0.6V to +14V
-0.6V to +7V
>2000V
Range
Commercial
Industrial
Temperature
0°C to +70°C
-40°C to +85°C
V
CC
3.3V
3.3V
Tolerance
±0.3V
±0.3V
DC Electrical Characteristics
Over Operating Range with V
PP
= V
CC
Symbol
V
IL
V
IH
V
OL1
V
OH1
V
OL2
V
OH2
I
SB1
I
SB2
I
CC
I
PP
V
PP
I
LI
I
LO
Parameter
Input Low Level
Input High Level
Output Low Voltage (TTL)
Output High Voltage (TTL)
Output Low Voltage
Output High Voltage (CMOS)
V
CC
Standby Current
(CMOS)
V
CC
Standby Current (TTL)
V
CC
Active Current
V
PP
Supply Current
V
PP
Read Voltage
Input Load Current
Output Leakage Current
Test Conditions
Min
-0.3
2.0
Max
0.7
V
CC
+ 0.3
0.4
Units
V
V
V
V
I
OL
= 2.0 mA
I
OH
= -2.0 mA
I
OL
= 100
µA
I
OH
= -100
µA
CE = V
CC
±
0.3V
CE = V
IH
CE = OE = V
IL
,
I/O = 0
µA
V
PP
= V
CC
V
CC
- 0.7
V
IN
= 3.0V or GND
V
OUT
= 3.0V or GND
-1
f = 5 MHz
V
CC
- 0.3
2.4
0.2
V
50
100
15
10
V
CC
1
10
µA
µA
mA
µA
V
µA
µA
AC Electrical Characteristics
Over Operating Range with V
PP
= V
CC
Symbol
t
ACC
t
CE
t
OE
t
DF
(Note 2)
t
OH
(Note 2)
Parameter
Min
Address to Output Delay
CE to Output Delay
OE to Output Delay
Output Disable to Output Float
Output Hold from Addresses,
CE or OE , Whichever
Occurred First
200
Max
200
200
70
50
250
Min
Max
250
250
75
50
Units
ns
0
0
3
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NM27LV010 1,048,576-Bit (128k x 8) Low Voltage EPROM
Capacitance
(Note 2) T
A
= +25°C, 1 = 1 MHz
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ
9
12
Max
15
15
Units
pF
pF
AC Test Conditions
Output Load
1 TTL Gate and C
L
= 100 pF (Note 8)
≤5
ns
0.45V to 2.4V
0.8V and 2V
0.8V and 2V
Input Rise and Fall Times
Input Pulse Levels
Timing Measurement Reference Level
Inputs
Outputs
AC Waveforms
(Note 6) , (Note 7) , and (Note 9)
ADDRESS
2.0V
0.8V
2.0V
0.8V
Address Valid
CE
OE
2.0V
0.8V
OUTPUT
2.0V
0.8V
t ACC
(Note 3)
Note 1:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operations sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Note 2:
This parameter is only sampled and is not 100% tested.
Note 4:
The t
DF
and t
CF
compare level is determined as follows:
High to TRI-STATE
®
, the measured V
OH1
(DC) - 0.10V;
Low to TRI-STATE, the measured V
OL1
(DC) + 0.10V.
Note 5:
TRI-STATE may be attained using OE or CE .
Note 6:
The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.2
µF
ceramic capacitor be used on every device
between V
CC
and GND.
Note 7:
The outputs must be restricted to V
CC
+ 1.0V to avoid latch-up and device damage.
Note 8:
1 TTL Gate: I
OL
= 1.6 mA, I
OH
= -400
µA.
C
L
: 100pF includes fixture capacitance.
Note 9:
V
PP
may be connected to V
CC
except during programming.
Note 10:
Inputs and outputs can undershoot to -2.0V for 20 ns Max.
Note 3:
OE may be delayed up to t
ACC
- t
CE
after the falling edge of CE without impacting t
ACC
.
,
,,
t CF
t CE
(Note 2, 4, 5)
t OE
(Note 3)
t DF
(Note 2, 4, 5)
Valid Output
Hi-Z
t OH
4
DS011377-3
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NM27LV010 1,048,576-Bit (128k x 8) Low Voltage EPROM
Programming Characteristics
(Note 11), (Note 12), (Note 13) and (Note 14)
Symbol
t
AS
t
OES
t
CES
t
DS
t
VPS
t
VCS
t
AH
t
DH
t
DF
t
PW
t
OE
I
PP
I
CC
T
A
V
CC
V
PP
t
FR
V
IL
V
IH
t
IN
t
OUT
Parameter
Address Setup Time
OE Setup Time
CE Setup Time
Data Setup Time
V
PP
Setup Time
V
CC
Setup Time
Address Hold Time
Data Hold Time
Output Enable to Output
Float Delay
Program Pulse Width
Data Valid from OE
V
PP
Supply Current
during Programming Pulse
V
CC
Supply Current
Temperature Ambient
Power Supply Voltage
Programming Supply Voltage
Input Rise, Fall Time
Input Low Voltage
Input High Voltage
Input Timing Reference Voltage
Output Timing Reference Voltage
Conditions
Min
1
1
1
1
1
1
0
1
Typ
Max
Units
µs
µs
µs
µs
µs
µs
µs
µs
CE/PGM = V
IL
0
45
50
60
105
100
20
20
ns
µs
ns
mA
mA
°C
V
V
ns
CE/PGM = V
IL
CE/PGM = V
IL
20
6.25
12.5
5
25
6.5
12.75
30
6.75
13.0
0.0
2.4
0.8
0.8
4.0
0.45
V
V
2.0
2.0
V
V
Programming Waveform
(Note 13)
Program
Addresses
2.0V
0.8V
t AS
2.0V
Data
0.8V
t DS
Data In Stable
ADD N
t DH
t DF
VCC
VPP
6.25V
t VCS
t VPS
Hi-Z
Address N
t AH
Data Out Valid
ADD N
Program Verify
12.75V
CE
t CES
PGM
2.0V
0.8V
t PW
tOES
tOE
OE
2.0V
0.8V
DS011377-4
Note 11:
Fairchild’s standard product warranty applies to devices programmed to specifications described herein.
Note 12:
V
CC
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
. The EPROM must not be inserted into or removedfrom a board with
voltage applied to V
PP
or V
CC
.
Note 13:
The maximum absolute allowable voltage which may be applied to the V
PP
pin during programming is 14V. Care must be taken when switching the V
PP
supply to
prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1
µF
capacitor is required across V
PP
, V
CC
to GND to suppress spurious voltage transients
which may damage the device.
Note 14:
During power up the PGM pin must be brought high (≥ V
IH
) either coincident with or before power is applied to V
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