NetChip
Technology, Inc.
335 Pioneer Way
Mt View, California 94041
(650) 526-1490 Fax (650) 526-1494
e-mail: sales@netchip.com
Internet: www.netchip.com
NET2272 USB 2.0 Peripheral Controller
Patent Pending
For Revision 1A
Doc #: 605-0213-0110
Revision: 1.2
Date: October 15, 2003
Specification
NET2272 USB Peripheral Controller
This document contains material that is confidential to NetChip. Reproduction without the express written consent
of NetChip is prohibited. All reasonable attempts were made to ensure the contents of this document are accurate,
however no liability, expressed or implied is guaranteed. NetChip reserves the right to modify this document,
without notification, at any time.
Revision History
Revision
1.0
1.1
1.2
Issue Date
May 5, 2003
October 7, 2003
October 15, 2003
Comments
Revision 1 silicon initial release
Revision 1.1 silicon release
Power consumption update
______________________________________________________________________________
NetChip Technology, Inc., 2003
Patent Pending
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490 FAX (650) 526-1494
http://www.netchip.com
Rev 1.2, October 15, 2003
2
Specification
NET2272 USB Peripheral Controller
NET2272 USB Peripheral Controller
1
INTRODUCTION .................................................................................................................................8
1.1
1.2
1.3
1.4
1.5
1.5.1
1.5.2
F
EATURES
.....................................................................................................................................8
O
VERVIEW
....................................................................................................................................8
NET2272 B
LOCK
D
IAGRAM
.......................................................................................................10
NET2272 T
YPICAL
S
YSTEM
B
LOCK
D
IAGRAMS
.........................................................................10
E
XAMPLE CONNECTIONS TO
NET2272........................................................................................12
Example Part Numbers..........................................................................................................13
General PCB Layout Guidelines ...........................................................................................13
USB Differential Signals..................................................................................................................13
Analog VDD (power).......................................................................................................................13
Analog VSS (ground).......................................................................................................................14
Decoupling Capacitors .....................................................................................................................14
EMI Noise Suppression....................................................................................................................14
1.5.2.1
1.5.2.2
1.5.2.3
1.5.2.4
1.5.2.5
1.6
2
T
ERMINOLOGY
............................................................................................................................14
PIN DESCRIPTION............................................................................................................................15
2.1
2.2
2.3
2.4
2.5
D
IGITAL
P
OWER
& G
ROUND
(10
PINS
)........................................................................................15
USB T
RANSCEIVER
(15
PINS
)......................................................................................................16
C
LOCKS
, R
ESET
, M
ISC
. (8
PINS
)..................................................................................................17
L
OCAL
B
US
P
IN
D
ESCRIPTIONS
(31
PINS
) ....................................................................................18
P
HYSICAL
P
IN
A
SSIGNMENT
........................................................................................................19
3
RESET AND INITIALIZATION.......................................................................................................20
3.1
3.2
3.3
3.4
O
VERVIEW
..................................................................................................................................20
RESET# P
IN
...............................................................................................................................20
R
OOT
P
ORT
R
ESET
......................................................................................................................20
R
ESET
S
UMMARY
........................................................................................................................20
4
LOCAL BUS INTERFACE................................................................................................................21
4.1
4.2
4.2.1
4.2.2
4.2.3
4.3
4.4
4.5
4.5.1
4.5.2
4.5.3
4.5.4
4.5.5
I
NTRODUCTION
............................................................................................................................21
R
EGISTER
A
DDRESSING
M
ODES
..................................................................................................21
Direct Address Mode .............................................................................................................21
Indirect Address Mode...........................................................................................................21
Multiplexed Address Mode ....................................................................................................21
C
ONTROL
S
IGNAL
D
EFINITIONS
..................................................................................................21
B
US
W
IDTH
/ B
YTE
A
LIGNMENT
.................................................................................................21
I/O T
RANSACTIONS
.....................................................................................................................22
Non-Multiplexed I/O Read.....................................................................................................22
Multiplexed I/O Read.............................................................................................................22
Non-Multiplexed I/O Write ....................................................................................................23
Multiplexed I/O Write ............................................................................................................23
I/O Performance ....................................................................................................................24
Non-Multiplexed Read Transaction .................................................................................................24
Multiplexed Read Transaction .........................................................................................................24
Non-Multiplexed Write Transaction ................................................................................................24
Multiplexed Write Transaction ........................................................................................................24
4.5.5.1
4.5.5.2
4.5.5.3
4.5.5.4
4.6
DMA T
RANSACTIONS
.................................................................................................................25
4.6.1
DMA Read .............................................................................................................................25
4.6.1.1
4.6.1.2
4.6.1.3
Slow DMA Read Timing .................................................................................................................26
Fast DMA Read Timing...................................................................................................................26
Burst DMA Read Timing.................................................................................................................26
4.6.2
4.6.2.1
DMA Write.............................................................................................................................27
Slow DMA Write Timing ................................................................................................................28
______________________________________________________________________________
NetChip Technology, Inc., 2003
Patent Pending
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490 FAX (650) 526-1494
http://www.netchip.com
Rev 1.2, October 15, 2003
3
Specification
4.6.2.2
4.6.2.3
NET2272 USB Peripheral Controller
Fast DMA Write Timing ..................................................................................................................28
Burst DMA Write Timing ................................................................................................................28
4.6.3
4.6.4
4.6.5
4.6.5.1
4.6.5.2
4.6.5.3
4.6.5.4
4.6.5.5
4.6.5.6
DMA Split Bus Mode .............................................................................................................29
Terminating DMA Transfers..................................................................................................29
DMA Performance.................................................................................................................30
DMA Read; Slow Mode...................................................................................................................30
DMA Read; Fast Mode ....................................................................................................................30
DMA Read; Burst Mode ..................................................................................................................30
DMA Write; Slow Mode..................................................................................................................30
DMA Write; Fast Mode ...................................................................................................................30
DMA Write; Burst Mode .................................................................................................................31
5
USB FUNCTIONAL DESCRIPTION ...............................................................................................32
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.3.1
5.3.2
5.4
5.5
5.6
5.6.1
5.6.2
5.6.2.1
5.6.2.2
USB I
NTERFACE
.........................................................................................................................32
USB P
ROTOCOL
..........................................................................................................................32
Tokens....................................................................................................................................32
Packets...................................................................................................................................32
Transaction ............................................................................................................................33
Transfer .................................................................................................................................33
A
UTOMATIC
R
ETRIES
..................................................................................................................33
Out Transactions ...................................................................................................................33
In Transactions ......................................................................................................................33
P
ING
F
LOW
C
ONTROL
..................................................................................................................33
P
ACKET
S
IZES
.............................................................................................................................33
USB E
NDPOINTS
.........................................................................................................................34
Control Endpoint - Endpoint 0 ..............................................................................................34
Control Write Transfer .....................................................................................................................34
5.6.1.1
Control Write Transfer Details..............................................................................................35
Control Read Transfer......................................................................................................................36
Control Read Transfer Details..........................................................................................................36
5.6.3
5.6.3.1
5.6.3.2
5.6.3.3
5.6.3.4
Isochronous Endpoints ..........................................................................................................37
Isochronous Out Transactions ..........................................................................................................38
High Bandwidth Isochronous OUT Transactions.............................................................................38
Isochronous In Transactions.............................................................................................................39
High Bandwidth Isochronous IN Transactions.................................................................................39
5.6.4
5.6.4.1
5.6.4.2
Bulk Endpoints.......................................................................................................................40
Bulk Out Transactions......................................................................................................................40
Bulk In Endpoints ............................................................................................................................41
5.6.5
5.6.5.1
5.6.5.2
5.6.5.3
Interrupt Endpoints................................................................................................................42
Interrupt Out Transactions ...............................................................................................................42
Interrupt In Endpoints ......................................................................................................................42
High Bandwidth INTERRUPT Endpoints .......................................................................................42
5.7
N
ET
C
HIP
V
IRTUAL
E
NDPOINTS
...................................................................................................43
5.7.1
Overview:...............................................................................................................................43
5.7.2
Endpoint Virtualization..........................................................................................................43
5.7.3
Efficiency Considerations:.....................................................................................................44
5.7.4
Deadlock Considerations: .....................................................................................................45
5.7.5
Buffer Control........................................................................................................................45
5.7.6
Summary ................................................................................................................................45
5.8
P
ACKET
B
UFFERS
........................................................................................................................46
5.8.1
IN Endpoint Buffers ...............................................................................................................46
5.8.1.1
16-bit Post-Validation ......................................................................................................................47
5.8.2
OUT Endpoint Buffers ...........................................................................................................47
5.9
USB T
EST
M
ODES
......................................................................................................................48
6
INTERRUPT AND STATUS REGISTER OPERATION ...............................................................49
6.1
I
NTERRUPT
S
TATUS
R
EGISTERS
(IRQSTAT0, IRQSTAT1)........................................................49
______________________________________________________________________________
NetChip Technology, Inc., 2003
Patent Pending
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490 FAX (650) 526-1494
http://www.netchip.com
Rev 1.2, October 15, 2003
4
Specification
6.2
6.3
7
NET2272 USB Peripheral Controller
E
NDPOINT
R
ESPONSE
R
EGISTERS
(EPRSP_CLR, EPRSP_SET).................................................49
E
NDPOINT
S
TATUS
R
EGISTER
(EP_STAT0, EP_STAT1) ...........................................................49
POWER MANAGEMENT .................................................................................................................50
7.1
S
USPEND
M
ODE
...........................................................................................................................50
7.1.1
The Suspend Sequence ...........................................................................................................50
7.1.2
Host-Initiated Wake-Up.........................................................................................................51
7.1.3
Device-Remote Wake-Up.......................................................................................................51
7.1.4
Resume Interrupt ...................................................................................................................51
7.2
NET2272 P
OWER
C
ONFIGURATION
............................................................................................51
7.2.1
Self-Powered Device..............................................................................................................51
7.2.2
Low-Power Modes .................................................................................................................51
7.2.2.1
7.2.2.2
USB Suspend (Unplugged from USB).............................................................................................51
Power-On Standby ...........................................................................................................................52
8
CONFIGURATION REGISTERS.....................................................................................................53
8.1
R
EGISTER
D
ESCRIPTION
..............................................................................................................53
8.2
R
EGISTER
S
UMMARY
...................................................................................................................53
8.2.1
Main Control Registers..........................................................................................................53
8.2.2
USB Control Registers...........................................................................................................54
8.2.3
Endpoint Registers.................................................................................................................54
8.3
N
UMERIC
R
EGISTER
L
ISTING
.......................................................................................................55
8.4
M
AIN
C
ONTROL
R
EGISTERS
........................................................................................................56
8.4.1
(Address 00h; REGADDRPTR) Indirect Register Address Pointer.......................................56
8.4.2
(Address 01h; REGDATA) Indirect Register Data ................................................................56
8.4.3
(Address 02h; IRQSTAT0) Interrupt Status Register (low byte)............................................56
8.4.4
(Address 03h; IRQSTAT1) Interrupt Status Register (high byte)...........................................57
8.4.5
(Address 04h; PAGESEL) Endpoint Page Select Register ....................................................57
8.4.6
(Address 1Ch; DMAREQ) DMA Request Control Register...................................................58
8.4.7
(Address 1Dh; SCRATCH) Scratchpad Register ...................................................................58
8.4.8
(Address 20h; IRQENB0) Interrupt Enable Register (low byte)............................................59
8.4.9
(Address 21h; IRQENB1) Interrupt Enable Register (high byte) ..........................................59
8.4.10 (Address 22h; LOCCTL) Local Bus Control Register ...........................................................60
8.4.11 (Address 23h; CHIPREV_LEGACY) Legacy Silicon Revision Register................................60
8.4.12 (Address 24h; LOCCTL1) Local Bus Control Register 1 ......................................................61
8.4.13 (Address 25h; CHIPREV_2272) Net2272 Silicon Revision Register.....................................61
8.5
USB C
ONTROL
R
EGISTERS
.........................................................................................................62
8.5.1
(Address 18h; USBCTL0) USB Control Register (low byte) .................................................62
8.5.2
(Address 19h; USBCTL1) USB Control Register (high byte) ................................................62
8.5.3
(Address 1Ah; FRAME0) Frame Counter (low byte) ............................................................62
8.5.4
(Address 1Bh; FRAME1) Frame Counter (high byte) ...........................................................62
8.5.5
(Address 30h; OURADDR) Our Current USB Address.........................................................63
8.5.6
(Address 31h; USBDIAG) USB Diagnostic Register.............................................................63
8.5.7
(Address 32h; USBTEST) USB Test Modes...........................................................................64
8.5.8
(Address 33h; XCVRDIAG) Transceiver Diagnostic Register ..............................................64
8.5.9
(Address 34h; VIRTOUT0) Virtual OUT 0 ............................................................................64
8.5.10 (Address 35h; VIRTOUT1) Virtual OUT 1 ............................................................................65
8.5.11 (Address 36h; VIRTIN0) Virtual IN 0 ....................................................................................65
8.5.12 (Address 37h; VIRTIN1) Virtual IN 1 ....................................................................................65
8.5.13 (Address 40h; SETUP0) Setup Byte 0....................................................................................65
8.5.14 (Address 41h; SETUP1) Setup Byte 1....................................................................................66
8.5.15 (Address 42h; SETUP2) Setup Byte 2....................................................................................66
8.5.16 (Address 43h; SETUP3) Setup Byte 3....................................................................................66
8.5.17 (Address 44h; SETUP4) Setup Byte 4....................................................................................66
8.5.18 (Address 45h; SETUP5) Setup Byte 5....................................................................................66
______________________________________________________________________________
NetChip Technology, Inc., 2003
Patent Pending
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490 FAX (650) 526-1494
http://www.netchip.com
Rev 1.2, October 15, 2003
5
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