BI-Phase/Dual Controller
POWER MANAGEMENT
Description
The SC2450 can be configured as a dual converter or a
bi-phase converter for high current applications. The part
is designed for point of use power supplies with 10-30V
nominal backplane power sources. Multiple supplies can
be synchronized together to prevent low frequency har-
monics on the backplane. The power dissipation is con-
trolled using a novel low voltage supply technique, allow-
ing high speed and integration, with the high drive cur-
rents to ensure low MOS.ET switching loss.
The use of high speed switching circuits allows very nar-
row PWM outputs down to 15:1 voltage ratios. Single
pin compensation for each channel simplifies develop-
ment as well as reducing external pin count.
Capable of driving MOS.ETs via external driver transis-
tors for phase currents beyond 20A.
SC2450
.eatures
K
K
K
K
K
K
K
K
K
Selectable dual output or bi-phase operation
Direct drive for N-channel MOS.ETs
Undervoltage lockout
Synchronization to external clock
Multi-converter synchronization
Soft start
.ast transient response
Max duty cycle 45%
Output over voltage protection
Applications
K
Power supplies for advanced telecoms/datacoms
K
SO IP, Ethernet and PABX power supplies
Typical Application Circuit
Revision 2, August 2001
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SC2450
POWER MANAGEMENT
Absolute Maximum Ratings
Parameter
Supply Voltage
Voltage on BST Pins
Oscillator Frequency
VC C
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering) 10 seconds
θ
JC
θ
J A
T
A
T
STG
T
LEAD
(1)
Symbol
V
IN
V
BST
Maximum
34
42
2
8
25
80
-40 to +85
-55 to +150
300
Units
V
V
MHz
V
°C/W
°C/W
°C
°C
°C
Note:
(1) Maximum frequency and maximum supply voltage could cause excessive power dissipation in the part.
Electrical Characteristics
Unless specified V
IN
= 24V, T
A
= 25°C
PARAMETER
Supply Voltage, V
IN
Supply Current
Under Voltage Lockout
UVLO Hysteresis
Voltage Regulator
Pre Regulator Voltage
Bgout Voltage
Bgout Impedance
REGDRV Pin Sink Current
Error Amp
Input Offset Voltage
Input Impedance
Linear Transconductance
Internal Oscillator
Frequency
Frequency
Ramp Valley to Peak
Ramp Valley to Peak
CONDITIONS
ENABLE = 0
MIN
10
TYP
30
5.8
400
MAX
30
40
UNITS
V
mA
V
mV
6
C
REF
= 4.7nF
I
REGDRV
0.99
1
3
5
7
1.01
V
V
KΩ
mA
10
5
.002
mV
KΩ
A/V
R
REF
= 30K
R
REF
= 60K
V
IN
= 12V
V
IN
= 24V
1
500
1.5
3
MHz
kHz
V
V
2001 Semtech Corp.
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SC2450
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified V
IN
= 24V, T
A
= 25°C
PARAMETER
External Clock
Detect Time
Unlock Time
Frequency Range
High Side Gate Drive
Max Duty Cycle
Peak Source
Peak Sink
Low Side Gate Drive
Peak Source
Peak Sink
Sync Drive Timing
Min Non-overlap
PWM Match
Logic Input Pins
Input Bias Current
Logic Threshold
FB2 Disable Threshold
Over Current Protection
OCP Threshold
OC+ I/P Bias Current
OC- I/P Bias Current
Over Voltage Protection
OVP Threshold
Thermal Shutdown
Note:
CONDITIONS
Rise Time < 50ns
MIN
TYP
MAX
2
UNITS
µs
µs
MHz
%
A
A
A
A
ns
10
0.3
45
C
LOAD
= 10nF
C
LOAD
= 10nF
C
LOAD
= 10nF
C
LOAD
= 10nF
C
LOAD
= 1nF Fet Drive < 1V
50% Duty Cycle, F
OSC
= 1MHz
V
IN
= 0 - 5V
20
-1
1
1
2
2
50
50
1
1
%
-10
0.8
V
CC
- 0.7V
103
115
700
50
10
µA
V
V
127
mV
µA
µA
V
IN
= 24V
120
150
%
°C
(1) This device is ESD sensitive. Use of standard ESD handling precautions is required.
2001 Semtech Corp.
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SC2450
POWER MANAGEMENT
Pin Configuration
Top View
Ordering Information
Part Number
(1)
SC2450ISWTR
S C 2450E V B
PACKAGE
T
AMB
(T
A
)
SO-28
-40 - +85°C
SC2450 Evaluation Board
Note:
(1) Only available in tape and reel packaging. A reel con-
tains 1000 devices.
(28-Pin SOIC)
Block Diagram
2001 Semtech Corp.
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SC2450
POWER MANAGEMENT
Pin Descriptions
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Pin Name
FB1
COMP1
NC
BG
FB2
COMP2
REGDRV
ENABLE
PHASE2
DRVH2
BSTH2
DRVL2
BSTL2
VCC
BSTL1
DRVL1
BSTH1
DRVH1
PHASE1
PGND
OC+
OC-2
OC-1
EXTCLK
CLKOUT
NC
AGND
RREF
Pin Function
Feedback for channel 1.
Compensation for channel 1.
No connection.
1V reference for error amplifiers, 3K source impedance.
Feedback for channel 2.
Compensation for channel 2.
Regulator drive for external pass transistor.
Enable threshold is 2.05 V, connect to ground to disable.
Phase node input for channel 2.
Gate drive for high side channel 2.
Bootstrap input for high side channel 2.
Gate drive for low side channel 2.
Supply for low side channel 2.
Pre-regulated IC power supply.
Supply for low side channel 1.
Gate drive for low side channel 1.
Bootstrap input for high side channel 1.
Gate drive for high side channel 1.
Phase node input for high side channel 1.
Power ground.
Overcurrent comparator inverting input.
Overcurrent comparator non-inverting input for channel 2.
Overcurrent comparator non-inverting input for channel 1.
External clock, converter locks to this input when a valid signal is present.
Clock out, logic level drive to provide synchronizing signal for other converters.
No connection.
Analog ground.
External reference resistor for internal oscillator and ramp generator.
2001 Semtech Corp.
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