INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
TENTATIVE
TOSHIBA RISC PROCESSOR
TMPR4925XB
(64-bit RISC MICROPROCESSOR)
1.
GENERAL DESCRIPTION
The TMPR4925XB, to be referred as TX4925 MIPS RISC micro-controller is a highly
integrated ASSP solution based on Toshiba’s TX49/H2 processor core, a 64-bit MIPS I,II,III
ISA Instruction Set Architecture (ISA) compatible with additional instructions. The TX4925
is a highly integrated device with integrated peripherals such as SDRAM memory controller,
NAND Flash memory controller, PCI controller, AC-Link controller, PIO, SIO, SPI, CHI,
PCMCIA I/F and Timer. This class of product is targeted for applications that require a high
performance and cost-effective solution such as networking, digital consumer and Internet
appliance.
2. FEATURES
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TX49/H2 core with an integrated IEEE 754-compliant FPU for single- and double-precision operations
4-channel SDRAM Controller ( 32bit/80MHz ) and support SyncFlash® memory
NAND Flash memory Controller
6-channel External Bus Controller
32-bit PCI Controller (33 MHz)
4-channel Direct Memory Access (DMA) Controller
2-channel Serial I/O Port
Parallel I/O Port (up to 32-bit)
AC-Link Controller ( AC97 Interface )
PCMCIA Interface (2-slot)
SPI (Serial Peripheral Interface)
CHI (high-speed serial Concentration Highway Interface)
Interrupt Controller
3-channel Timer/Counter and 44-bit up-counter RTC
Low power dissipation
The TX4925 operates with the 1.5V core and the 3.3V I/O, while supporting a low-power (Halt) mode.
CPU maximum operating frequency: 200 MHz
IEEE1149.1 (JTAG) support: Debug Support Unit (Enhanced JTAG)
256-pin PBGA package
- The products described in this document are subject to foreign exchange and foreign trade control laws.
- The information contained herein is subject to change without notice.
- TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when
utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product
could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most
recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability
Handbook.
EJC-TMPR4925XB-1
- The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
26/Dec/01 Rev 0.1
TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by
TOSHIBA CORPORATION
implication or otherwise under any patent or patent rights of TOSHIBA or others.
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
TENTATIVE
2.1 Internal Block Diagram
Figure 1 shows the TX4925 internal block diagram.
PLL
Debug (DSU)
G
D$(16K
)
NAND Flash C
SDRAMC
DMAC
32bit Gbus
IU
MMU
I$(16K)
GPR
MAC
BIU
WB
FPU
TX49/H2 CPU Core
|
B
U
S
External BUS
Controller
External BUS
Interface
(32bit)
PCIC
CHI
IM bus
bridge
IM bus
SIO
PIO
IRC
ACLC
SPI
RTC
Timer
Figure
2.1 TX4925 Internal Block Diagram
EJC-TMPR4925XB-2
26/Dec/01 Rev 0.1
TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
TENTATIVE
2.2 System Block Diagram
Figure 2.2 shows the system block diagram with TX4925.
32bit Gbus
PLL
NAND Flash C
SDRAMC
G
I
B
U
S
DMAC
External BUS
Controller
Command/Data/
Address signals
SDRAM Control
signals
NAND Flash Memory
SDRAM Memory
Devices
Debug (DSU)
D$(16K)
GPR
MAC
IU
MMU
WB
FPU
I$(16K)
BIU
External System Bus
(Data=32bit, Address=20bit)
External BUS
Interface
TX49/H2 CPU Core
PCIC
CHI
AC
Control
Signals
ROM/
Flash/
SRAM
External
I/O
Devices
IM bus
bridge
IM bus
SIO
PIO
IRC
ACLC
SPI
RTC
Timer
32
PCI Bus
PCI Devices
User logic
PCIC
Figure 2.2 Typical TX4925 System Block Diagram
EJC-TMPR4925XB-3
26/Dec/01 Rev 0.1
TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
TENTATIVE
2.3 TX49/H2 Core Block Diagram
Figure 3 shows the internal block diagram of the TX49/H2 core
TX49/H2 Core
Integer Unit
GPR
Data
Path
MAC
FPU
Pipeline
Control
CP0
CP0 Registers
MMU/TLB
Exception Unit
CP1
Debug
Support
Unit
16KB
4-way set
Instruction
Cache
Write
Buffer
16KB
4-way set
Data
Cache
Figure 2.3 TX49/H2 Core Block Diagram
2.4 TX49/H2 CORE FEATURES
The TX49/H2 Core is high performance and low-power 64-bit RISC processor core
developed by Toshiba.
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64-bit operation
32, 64-bit integer general purpose registers
32-bit physical address space and 64-bit virtual address space
Optimized 5-stage pipeline
Instruction Set
MIPS I, II , III compatible ISA
PREF (Prefetch) and MAC (Multiply/Accumulate) instructions.
16k Byte Instruction Cache, and 16k Byte Data Cache
4-way set associative with lock function
MMU (Memory Management Unit): 48-entry fully associative JTLB
The on-chip FPU supports both single- and double-precision arithmetic, as specified in
IEEE Std 754.
On-chip 4-deep write buffer
Enhanced JTAG debug feature
Built-in Debug Support Unit (DSU)
EJC-TMPR4925XB-4
26/Dec/01 Rev 0.1
TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
TENTATIVE
2.5 TX4925 Peripheral Circuit FEATURES
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External Bus Controller ( EBUSC )
The External Bus Controller generates necessary signals to control external memory and I/O
devices.
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6 channels of chip select signals, enabling control of up to six devices
(shared chip select signals of 2 channels)
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Supports access to ROM ( including mask ROM, page mode ROM, EPROM and
EEPROM), SRAM, flash ROM, and I/O devices
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Supports 32-bit, 16-bit and 8-bit data bus sizing on a per channel basis
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Supports selection among full speed (up to 80MHz ), 1/2 speed ( up to 40MHz), 1/3
speed ( up tp 27MHz ) and 1/4 speed ( up to 20MHz) on a per channel basis
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Support specification of timing on a per channel basis
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The user can specify setup and hold times for address, chip enable, write enable, and
output enable signals
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Supports memory sizes of 1M byte to 1G byte for devices with 32-bit data bus, 1M byte
to 512M bytes for devices with 16-bit data bus, and 1M byte to 256M bytes for devices
with 8-bit data bus
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DMA Controller ( DMAC )
The TX4925 contains a 4-channel DMA controller that executes DMA transfer to memory
and I/O devices.
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4-channel independently handling internal / external DMA requests
(Usable only 2 channels by external DMA requests)
Supports DMA transfer with built-in serial I/O controller and AC-link controller based on
internal DMA requests
Supports signal address ( fly-by DMA ) and dual address transfers in external I/O DMA
transfer mode using external DMA requests
Supports transfer between memory and external I/O devices having 32 / 16 / 8-bit data
bus
Supports memory-to-memory copy mode, with no address boundary restrictions
Supports burst transfer of up to 8 double words for a single read / write
Supports memory fill mode, writing double-word data to specified memory area
Supports chained DMA transfer
EJC-TMPR4925XB-5
26/Dec/01 Rev 0.1
TOSHIBA CORPORATION
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