IDT74LVC573AQ datasheet, PDF - EEWORLD Datasheet

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IDT74LVC573AQ: Description3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O; File Size60KB，6 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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IDT74LVC573AQ Overview

3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O

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IDT74LVC573A

3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH

INDUSTRIAL TEMPERATURE RANGE

3.3V CMOS OCTAL

TRANSPARENT D-TYPE LATCH

WITH 3-STATE OUTPUTS

AND 5 VOLT TOLERANT I/O

• 0.5 MICRON CMOS Technology

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

• V

= 3.3V ± 0.3V, Normal Range

• V

= 2.7V to 3.6V, Extended Range

• CMOS power levels (0.4µ W typ. static)

• Rail-to-rail output swing for increased noise margin

• All inputs, outputs, and I/O are 5V tolerant

• Supports hot insertion

• Available in SOIC, SSOP, QSOP, and TSSOP packages

IDT74LVC573A

FEATURES:

DESCRIPTION:

DRIVE FEATURES:

• High Output Drivers: ±24mA

• Reduced system switching noise

APPLICATIONS:

• 5V and 3.3V mixed voltage systems

• Data communication and telecommunication systems

The LVC573A octal transparent D-type latch is built using advanced dual

metal CMOS technology. The device features 3-state outputs designed

specifically for driving highly capacitive or relatively low-impedance loads,

and is particularly suitable for implementing buffer registers, input-output (I/

O) ports, bidirectional bus drivers, and working registers.

While the latch-enable (LE) input is high, the Q outputs follow the data

(D) inputs. When LE is taken low, the Q outputs are latched at the logic levels

at the D inputs.

A buffered output-enable (OE) input can be used to place the eight

outputs in either a normal logic state (high or low logic levels) or a high-

impedance state. In the high-impedance state, the outputs neither load nor

drive the bus lines significantly. The high-impedance state and increased

drive provide the capability to drive bus lines without interface or pullup

components.

does not affect the internal operations of the latch. Old data

can be retained or new data can be entered while the outputs are in the

high-impedance state.

The LVC573A has been designed with a ±24mA output driver. This

driver is capable of driving a moderate to heavy load while maintaining

speed performance.

Inputs can be driven from either 3.3V or 5V devices. This feature allows

the use of this device as a translator in a mixed 3.3V/5V system environ-

ment.

FUNCTIONAL BLOCK DIAGRAM

TO SEVEN OTHER CHANNELS

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

INDUSTRIAL TEMPERATURE RANGE

MARCH 1999

DSC-4627/1

IDT74LVC573AQ Related Products

	IDT74LVC573AQ	IDT74LVC573APY	IDT74LVC573ASO	IDT74LVC573A	IDT74LVC573APG
Description	3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O	3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O	3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O	3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O	3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O

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