TN80C186EB25 datasheet, PDF - EEWORLD Datasheet

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TN80C186EB25: Description16-BIT, 25 MHz, MICROPROCESSOR, PQFP80; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，59 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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TN80C186EB25 Overview

16-BIT, 25 MHz, MICROPROCESSOR, PQFP80

TN80C186EB25 Parametric

Parameter Name	Attribute value
Maker	Intel
Parts packaging code	LCC
package instruction	QCCJ,
Contacts	84
Reach Compliance Code	unknown
ECCN code	3A001.A.3
Other features	DRAM REFRESH CONTROLLER; 3 PROGRAMMABLE TIMERS; EMULATION HARDWARE; NUMERIC COPROCESSOR INTERFACE
Address bus width	20
bit size	16
boundary scan	NO
maximum clock frequency	50 MHz
External data bus width	16
Format	FIXED POINT
Integrated cache	NO
JESD-30 code	S-PQCC-J84
length	29.3 mm
low power mode	YES
Number of DMA channels
Number of external interrupt devices	6
Number of serial I/Os	2
Number of terminals	84
On-chip data RAM width
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Package shape	SQUARE
Package form	CHIP CARRIER
Certification status	Not Qualified
RAM (number of words)	0
Maximum seat height	4.83 mm
speed	25 MHz
Maximum slew rate	115 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
width	29.3 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR
Base Number Matches	1

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80C186EB/80C188E B AND 80L186EB/80L188EB

16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

■

Full Static Operation

■

True CMOS Inputs and Outputs

■

Integrate d Feature Set

■

Available in Extended Temperature

— Low-Power Static CPU Core

— Two Independent UARTs each with

an Integral Baud Rate Generator

— Two 8-Bit Multiplexed I/ O Ports

— Programmable Interrupt Controller

— Three Programmable 16-Bit

Timer/Counters

— Clock Generator

— Ten Programmable Chip Selects with

Integral Wait-State Generator

— Memory Refresh Control Unit

— System Level Testing Support (ONCE

Mode)

■

Speed Versions Available (3V):

■

Low-Power Operating Modes:

Range (

C to

— 16 MHz (80L186EB16/80L188EB16)

— 13 MHz (80L186EB13/80L188EB13)

■

Supports 80C187 Numeric Coprocessor

■

Available In:

Interface (80C186EB PLCC Only)

—80-Pin Quad Flat Pack (QFP)

—84-Pin Plastic Leaded Chip Carrier

(PLCC)

—80-Pin Shrink Quad Flat Pack (SQFP)

—Idle Mode Freezes CPU Clocks but

keeps Peripherals Active

—Powerdown Mode Freezes All

Internal Clocks

■

Direct Addressing Capability to 1 Mbyte

■

Speed Versions Available (5V):

Memory and 64 Kbyte I/O

— 25 MHz (80C186EB25/80C188EB25)

— 20 MHz (80C186EB20/80C188EB20)

— 13 MHz (80C186EB13/80C188EB13)

The 80C186EB is a second generation CHMOS High-Integration microprocessor. It has features that are new

to the 80C186 family and include a STATIC CPU core, an enhanced Chip Select decode unit, two independent

Serial Channels, I/O ports, and the capability of Idle or Powerdown low power modes.

272433– 1

* Other brands and names are the property of their respective owners.

Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or

copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make

changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

July, 2004

Order Number: 272433-006

INTEL CORPORATION, 2004

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