STF8NK100Z
STP8NK100Z
N-CHANNEL 1000V - 1.60Ω - 6.5A - TO-220 - TO-220FP
Zener-Protected SuperMESH™ MOSFET
General features
Type
V
DSS
R
DS(on)
I
D
Pw
STF8NK100Z 1000 V <1.85Ω 6.5 ANote 1 40 W
STP8NK100Z 1000 V <1.85Ω
6.5 A
160 W
■
■
■
■
EXTREMELY HIGH dv/dt CAPABILITY
3
3
1
2
100% AVALANCHE RATED
IMPROVED ESD CAPABILITY
VERY LOW INTRINSIC CAPACITANCE
TO-220
1
2
TO-220FP
Description
The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established
stripbased PowerMESH™ layout. In addition to
pushing on-resistance significantly down, special
care is taken to ensure a very good dv/dt
capability for the most demanding applications.
Such series complements ST full range of high
voltage
MOSFETs
including
revolutionary
MDmesh™ products.
Internal schematic diagram
Applications
■
■
HIGH CURRENT,SWITCHING APPLICATION
IDEAL FOR OFF-LINE POWER SUPPLIES
Order codes
Sales Type
STF8NK100Z
STP8NK100Z
Marking
F8NK100Z
P8NK100Z
Package
TO-220FP
TO-220
Packaging
TUBE
TUBE
November 2005
Rev 1
1/13
www.st.com
13
1 Electrical ratings
STF8NK100Z - STP8NK100Z
1
Table 1.
Electrical ratings
Absolute maximum ratings
Parameter
TO-220
V
DS
V
DGR
V
GS
I
D
Note
1
I
D
Drain-source Voltage (V
GS
=0)
Drain-gate Voltage
Gate-Source Voltage
Drain Current (continuous) at T
C
= 25°C
Drain Current (continuous) at T
C
= 100°C
Drain Current (pulsed)
Total Dissipation at T
C
= 25°C
Derating Factor
V
ESD(G-S)
Gate source ESD (HBM-C=100pF, R=1.5KΩ)
6.5
4.3
16
160
1.28
4000
4.5
--
-55 to 150
2500
1000
1000
± 30
6.5
4.3
16
40
0.32
Value
TO-220FP
V
V
V
A
A
A
W
W/°C
V
V/ns
V
°C
Unit
Symbol
I
DM
Note
2
P
TOT
dv/dt
Note
3 Peak Diode Recovery voltage slope
V
ISO
T
j
T
stg
Insulation Withstand Voltage (DC)
Operating Junction Temperature
Storage Temperature
Table 2.
Thermal data
TO-220
TO-220FP
3.1
62.5
300
°C/W
°C/W
°C
Rthj-case
Rthj-a
T
l
Thermal Resistance Junction-case Max
Thermal Resistance Junction-ambient Max
Maximum Lead Temperature For Soldering
Purpose
0.78
Table 3.
Symbol
I
AR
E
AS
Avalanche Characteristics
Parameter
Avalanche Current, Repetitive or
Not-Repetitive (pulse width limited by Tj max)
Single Pulse Avalanche Energy
(starting Tj= 25°C, I
D
=I
AR
, V
DD
=50V)
Value
6.5
320
Unit
A
mJ
2/13
STF8NK100Z - STP8NK100Z
2 Electrical characteristics
2
Electrical characteristics
(T
CASE
= 25 °C unless otherwise specified)
Table 4.
Symbol
V
(BR)DSS
I
DSS
On/off states
Parameter
Drain-Source Breakdown
Voltage
Zero Gate Voltage Drain
Current (V
GS
= 0)
Gate Body Leakage Current
(V
DS
= 0)
Gate Threshold Voltage
Static Drain-Source On
Resistance
Test Conditions
I
D
= 1mA, V
GS
= 0
V
DS
= Max Rating,
V
DS
= Max Rating,Tc = 125°C
V
GS
= ±20V
V
DS
= V
GS
, I
D
= 100 µA
V
GS
= 10 V, I
D
= 3.15 A
3
3.75
1.60
Min.
1000
1
50
±
10
Typ.
Max.
Unit
V
µA
µA
µA
V
Ω
I
GSS
V
GS(th)
R
DS(on)
4.5
1.85
Table 5.
Symbol
g
fs
Note
6
C
iss
C
oss
C
rss
C
oss eq.
Note
5
Q
g
Q
gs
Q
gd
Dynamic
Parameter
Forward Transconductance
Test Conditions
V
DS
=15V, I
D
=3.15 A
Min.
Typ.
7
2180
174
36
83
73
12
40
102
Max.
Unit
S
pF
pF
pF
pF
nC
nC
nC
Input Capacitance
V
DS
=25V, f=1 MHz, V
GS
=0
Output Capacitance
Reverse Transfer Capacitance
Equivalent Output
Capacitance
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
GS
=0V, V
DS
=0 to 800V
V
DD
=800V, I
D
= 6.3A
V
GS
=10V
(see Figure 17)
3/13
2 Electrical characteristics
STF8NK100Z - STP8NK100Z
Table 6.
Symbol
t
d(on)
t
r
t
d(off)
t
f
Switching times
Parameter
Turn-on Delay Time
Rise Time
Test Conditions
V
DD
=500 V, I
D
= 3.15 A,
R
G
=4.7Ω, V
GS
=10V
(see Figure 18)
V
DD
=500 V, I
D
=3.15 A,
R
G
=4.7Ω, V
GS
=10V
(see Figure 18)
Min.
Typ.
28
19
Max.
Unit
ns
ns
Turn-off Delay Time
FallTime
59
30
ns
ns
Table 7.
Symbol
I
SD
I
SDM
Note
3
V
SD
Note
2
t
rr
Q
rr
I
RRM
t
rr
Q
rr
I
RRM
Source drain diode
Parameter
Source-drain Current
Source-drain Current (pulsed)
Forward on Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
I
SD
=6.3A, V
GS
=0
I
SD
=6.3A, di/dt = 100A/µs,
V
DD
=50 V, Tj=25°C
620
5.3
17
840
7.5
18
Test Conditions
Min.
Typ.
Max.
6.5
26
1.6
Unit
A
A
V
ns
µC
A
ns
µC
A
I
SD
=6.3A, di/dt = 100A/µs,
V
DD
=50 V, Tj=150°C
Table 8.
Symbol
BV
GSO
Note
4
Gate-source zener diode
Parameter
Gate-Source Breakdown
Voltage
Test Conditions
Igs = ± 1mA (Open Drain)
Min.
30
Typ.
Max.
Unit
V
(1) Limited only by maximum temperature allowed
(2)I
SD
≤
6.5 A, di/dt
≤
200A/µs, V
DS
≤
V
(BR)DSS,
Tj≤ Tjmax
(3) Pulse width limited by safe operating area
(4) The built-in-back-to-back Zener diodes have specifically been designed to enanche not only the device’s ESD capability, but
also to make them safely absorb possible voltage is appropriate to archieve an efficient and cost-effective intervention to
protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components.
(5) C
oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C
oss
when V
DS
increases from 0
to 80% V
DSS
(6) Pulsed: pulse duartion = 300µs, duty cycle 1.5%
4/13
STF8NK100Z - STP8NK100Z
2 Electrical characteristics
2.1
Electrical characteristics (curves)
Safe Operating Area for TO-220
Figure 2.
Thermal Impedance for TO-220
Figure 1.
Figure 3.
Safe Operating Area for TO-220FP
Figure 4.
Thermal Impedance for TO-220FP
Figure 5.
Output Characteristics
Figure 6.
Transfer Characteristics
5/13
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