Multichannel ISM Band
FSK/GFSK/OOK/GOOK/ASK Transmitter
ADF7012
FEATURES
Single-chip, low power UHF transmitter
75 MHz to 1 GHz frequency operation
Multichannel operation using fractional-N PLL
2.3 V to 3.6 V operation
On-board regulator
Programmable output power
−16 dBm to +14 dBm, 0.4 dB steps
Data rates: dc to 179.2 kbps
Low current consumption
868 MHz, 10 dBm, 21 mA
433 MHz, 10 dBm, 17 mA
315 MHz, 0 dBm, 10 mA
Programmable low battery voltage indicator
24-lead TSSOP
GENERAL DESCRIPTION
The ADF7012 is a low power FSK/GFSK/OOK/GOOK/ASK
UHF transmitter designed for short-range devices (SRDs). The
output power, output channels, deviation frequency, and mod-
ulation type are programmable by using four, 32-bit registers.
The fractional-N PLL and VCO with external inductor enable
the user to select any frequency in the 75 MHz to 1 GHz band.
The fast lock times of the fractional-N PLL make the ADF7012
suitable in fast frequency hopping systems. The fine frequency
deviations available and PLL phase noise performance facilitates
narrow-band operation.
There are five selectable modulation schemes: binary frequency
shift keying (FSK), Gaussian frequency shift keying (GFSK),
binary on-off keying (OOK), Gaussian on-off keying (GOOK),
and amplitude shift keying (ASK). In the compensation register,
the output can be moved in <1 ppm steps so that indirect com-
pensation for frequency error in the crystal reference can be made.
A simple 3-wire interface controls the registers. In power-down,
the part has a typical quiescent current of <0.1 μA.
APPLICATIONS
Low cost wireless data transfer
Security systems
RF remote controls
Wireless metering
Secure keyless entry
FUNCTIONAL BLOCK DIAGRAM
PRINTED
INDUCTOR
OSC1
OSC2
CLK
OUT
L1
L2
C
VCO
OOK\ASK
÷CLK
VCO
PA
DV
DD
÷R
PFD/
CHARGE
PUMP
V
DD
RF
OUT
RF
GND
DGND
LDO
REGULATOR
C
REG
OOK\ASK
TxCLK
+FRACTIONAL N
TxDATA
LE
DATA
CLK
FSK\GFSK
Σ-Δ
PLL LOCK
DETECT
BATTERY
MONITOR
MUXOUT
R
SET
04617-0-001
SERIAL
INTERFACE
FREQUENCY
COMPENSATION
CENTER
FREQUENCY
MUXOUT
CE
AGND
Figure 1.
Rev. A
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
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Fax: 781.461.3113 ©2007–2009 Analog Devices, Inc. All rights reserved.
ADF7012
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics..................................................................... 5
Absolute Maximum Ratings............................................................ 6
Transistor Count ........................................................................... 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
315 MHz ........................................................................................ 8
433 MHz ........................................................................................ 9
868 MHz ...................................................................................... 10
Circuit Description ......................................................................... 12
PLL Operation ............................................................................ 12
Crystal Oscillator ........................................................................ 12
Crystal Compensation Register ................................................ 12
Clock Out Circuit ....................................................................... 12
Loop Filter ................................................................................... 13
Voltage-Controlled Oscillator (VCO) ..................................... 13
Voltage Regulators ...................................................................... 13
FSK Modulation.......................................................................... 13
GFSK Modulation ...................................................................... 14
Power Amplifier ......................................................................... 14
GOOK Modulation .................................................................... 15
Output Divider ........................................................................... 16
MUXOUT Modes....................................................................... 16
Theory of Operation ...................................................................... 17
Choosing the External Inductor Value .................................... 17
Choosing the Crystal/PFD Value ............................................. 17
Tips on Designing the Loop Filter ........................................... 18
PA Matching................................................................................ 18
Transmit Protocol and Coding Considerations ..................... 18
Application Examples .................................................................... 19
315 MHz Operation ................................................................... 20
433 MHz Operation ................................................................... 21
868 MHz Operation ................................................................... 22
915 MHz Operation ................................................................... 23
Register Descriptions ..................................................................... 24
Register 0: R Register ................................................................. 24
Register 1: N-Counter Latch ..................................................... 25
Register 2: Modulation Register ............................................... 26
Register 3: Function Register .................................................... 27
Outline Dimensions ....................................................................... 28
Ordering Guide .......................................................................... 28
REVISION HISTORY
6/09—Rev.
0 to Rev. A
Updated Format .................................................................. Universal
Changes to Table 4 ............................................................................ 7
Changes to Crystal Oscillator Section ......................................... 12
Changes to Loop Filter Section ..................................................... 13
Changes to GFSK Modulation Section ........................................ 14
Changes to Choosing the External Inductor Value Section ..... 17
Changes to Component Values—Crystal: 3.6864 MHz ............ 20
Changes to Component Values—Crystal: 4.9152 MHz ............ 21
Changes to Component Values—Crystal: 4.9152 MHz ............ 22
Changes to Component Values—Crystal: 10 MHz.................... 23
Added Register Headings Throughout ........................................ 24
Changes to Ordering Guide .......................................................... 28
10/04—Revision 0: Initial Version
Rev. A | Page 2 of 28
ADF7012
SPECIFICATIONS
DV
DD
= 2.3 V – 3.6 V; AGND = DGND = 0 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted. Operating temperature range is −40°C to +85°C.
Table 1.
Parameter
RF OUTPUT CHARACTERISTICS
Operating Frequency
Phase Frequency Detector
MODULATION PARAMETERS
Data Rate FSK/GFSK
Data Rate ASK/OOK
Deviation FSK/GFSK
GFSK BT
ASK Modulation Depth
OOK Feedthrough (PA Off )
POWER AMPLIFIER PARAMETERS
Maximum Power Setting, DV
DD
= 3.6 V
Maximum Power Setting, DV
DD
= 3.0 V
Maximum Power Setting, DV
DD
= 2.3 V
Maximum Power Setting, DV
DD
= 3.6 V
Maximum Power Setting, DV
DD
= 3.0 V
Maximum Power Setting, DV
DD
= 2.3 V
PA Programmability
POWER SUPPLIES
DV
DD
Current Consumption
315 MHz, 0 dBm/5 dBm
433 MHz, 0 dBm/10 dBm
868 MHz, 0 dBm/10 dBm/14 dBm
915 MHz, 0 dBm/10 dBm/14 dBm
VCO Current Consumption
Crystal Oscillator Current
Consumption
Regulator Current Consumption
Power-Down Current
REFERENCE INPUT
Crystal Reference Frequency
Single-Ended Reference Frequency
Crystal Power-On Time 3.4 MHz/26
MHz
Single-Ended Input Level
B Version
75/1000
F
RF
/128
179.2
64
PFD/2
14
511 × PFD/2
14
0.5
25
−40
−80
14
13.5
12.5
14.5
14
13
0.4
2.3/3.6
8/14
10/18
14/21/32
16/24/35
1/8
190
280
0.1/1
3.4/26
3.4/26
1.8/2.2
CMOS levels
Unit
Conditions/Comments
MHz min/max VCO range adjustable using external inductor; divide-by-2, -4, -8
options may be required
Hz min
kbps
Kbps
Hz min
Hz max
typ
dB max
dBm typ
dBm typ
dBm
dBm
dBm
dBm
dBm
dBm
dB typ
V min/V max
mA typ
mA typ
mA typ
mA typ
mA min/max
μA typ
μA typ
μA typ/max
MHz min/max
MHz min/max
ms typ
CE to clock enable valid
Refer to the LOGIC INPUTS parameter. Applied OSC 2,
oscillator circuit disabled.
DV
DD
= 3.0 V, PA is matched into 50 Ω, I
VCO
= min
Using 1 MHz loop bandwidth
Based on US FCC 15.247 specifications for ACP; higher data rates
are achievable depending on local regulations
For example, 10 MHz PFD − deviation min = ±610 Hz
For example, 10 MHz PFD − deviation max = ±311.7 kHz
F
RF
= F
VCO
F
RF
= F
VCO
/2
F
RF
= 915 MHz, PA is matched into 50 Ω
F
RF
= 915 MHz, PA is matched into 50 Ω
F
RF
= 915 MHz, PA is matched into 50 Ω
F
RF
= 433 MHz, PA is matched into 50 Ω
F
RF
= 433 MHz, PA is matched into 50 Ω
F
RF
= 433 MHz, PA is matched into 50 Ω
PA output = −20 dBm to +13 dBm
VCO current consumption is programmable
Rev. A | Page 3 of 28
ADF7012
Parameter
PHASE-LOCKED LOOP PARAMETERS
VCO Gain
315 MHz
433 MHz
868 MHz
915 MHz
VCO Tuning Range
Spurious (IVCO Min/Max)
Charge Pump Current
Setting [00]
Setting [01]
Setting [10]
Setting [11]
Phase Noise (In band)
1
315 MHz
433 MHz
868 MHz
915 MHz
Phase Noise (Out of Band)
1
315 MHz
433 MHz
868 MHz
915 MHz
Harmonic Content (Second)
2
Harmonic Content (Third)
2
Harmonic Content (Others)
2
Harmonic Content (Second)
2
Harmonic Content (Third)
2
Harmonic Content (Others)
2
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
INH
/I
INL
Input Capacitance, C
IN
LOGIC OUTPUTS
Output High Voltage, V
OH
Output High Current, I
OH
,
Output Low Voltage, V
OL
1
2
B Version
Unit
Conditions/Comments
22
24
80
88
0.3/2.0
−65/−70
0.3
0.9
1.5
2.1
−85
−83
−80
−80
−103
−104
−115
−114
−20
−30
−27
−24
−14
−19
0.7 × DV
DD
0.2 × DV
DD
±1
4.0
DV
DD
− 0.4
500
0.4
MHz/V typ
MHz/V typ
MHz/V typ
MHz/V typ
V min/max
dBc
mA typ
mA typ
mA typ
mA typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
V min
V max
μA max
pF max
V min
μA max
V max
VCO divide-by-2 active
VCO divide-by-2 active
I
VCO
is programmable
Referring to DB[7:6] in Function Register
Referring to DB[7:6] in Function Register
Referring to DB[7:6] in Function Register
Referring to DB[7:6] in Function Register
PFD = 10 MHz, 5 kHz offset, I
VCO
= 2 mA
PFD = 10 MHz, 5 kHz offset, I
VCO
= 2 mA
PFD = 10 MHz, 5 kHz offset, I
VCO
= 3 mA
PFD = 10 MHz, 5 kHz offset, I
VCO
= 3 mA
PFD = 10 MHz, 1 MHz offset, I
VCO
= 2 mA
PFD = 10 MHz, 1 MHz offset, I
VCO
= 2 mA
PFD = 10 MHz, 1 MHz offset, I
VCO
= 3 mA
PFD = 10 MHz, 1 MHz offset, I
VCO
= 3 mA
F
RF
= F
VCO
F
RF
= F
VCO
/N (where N = 2, 4, 8)
CMOS output chosen
I
OL
= 500 μA
Measurements made with N
FRAC
= 2048.
Measurements made without harmonic filter.
Rev. A | Page 4 of 28
ADF7012
TIMING CHARACTERISTICS
DV
DD
= 3 V ± 10%; AGND = DGND = 0 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
t
1
t
2
t
3
t
4
t
5
t
6
t
7
Limit at T
MIN
to T
MAX
(B Version)
20
10
10
25
25
10
20
t
4
CLK
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
t
5
Test Conditions/Comments
LE setup time
Data-to-clock setup time
Data-to-clock hold time
Clock high duration
Clock low duration
Clock-to-LE setup time
LE pulse width
t
2
DATA
DB23 (MSB)
DB22
t
3
DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t
7
LE
t
1
LE
t
6
04617-0-002
Figure 2. Timing Diagram
Rev. A | Page 5 of 28
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