Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic array
(22
×
42
×
10)
PLUS173–10
DESCRIPTION
The PLUS173–10 PLD is a high speed,
combinatorial Programmable Logic Array.
The Philips Semiconductors state-of-the-art
Oxide Isolated Bipolar fabrication process is
employed to produce maximum propagation
delays of 10ns or less.
The 24-pin PLUS173–10 device has a
programmable AND array and a
programmable OR array. Unlike PAL
®
devices, 100% product term sharing is
supported. Any of the 32 logic product terms
can be connected to any or all of the 10
output OR gates. Most PAL ICs are limited to
7 AND terms per OR function; the
PLUS173–10 device can support up to 32
input wide OR functions.
The polarity of each output is user-
programmable as either Active-High or
Active-Low, thus allowing AND-OR or
AND-NOR logic implementation. This feature
adds an element of design flexibility,
particularly when implementing complex
decoding functions.
The PLUS173–10 device is user-
programmable using one of several
commercially available, industry standard
PLD programmers.
FEATURES
•
I/O propagation delays
–
10ns (worst case)
PIN CONFIGURATIONS
N Package
I0 1
I1 2
I2 3
I3 4
I4 5
I5 6
I6 7
I7 8
I8 9
I9 10
I10 11
GND 12
24 V
CC
23 B9
22 B8
21 B7
20 B6
19 B5
18 B4
17 B3
16 B2
15 B1
14 B0
13 I11
•
Functional superset of 20L10 and most
other 24-pin combinatorial PAL devices
•
Two programmable arrays
–
Supports 32 input wide OR functions
•
12 inputs
•
10 bi-directional I/O
•
42 AND gates
–
32 logic product terms
–
10 direction control terms
•
Programmable output polarity
–
Active-High or Active-Low
•
Security fuse
•
3-State outputs
•
Power dissipation: 850mW (typ.)
•
TTL Compatible
APPLICATIONS
N = Plastic Dual In-Line (300mil-wide)
A Package
I3
4
NC 5
I4 6
I5 7
I6 8
I7 9
I8 10
NC 11
12
I9
13
14
15
16
17
18
I2
3
I1
2
I0 V
CC
B9 B8
1 28 27 26
25 NC
24 B7
23 B6
22 B5
21 B4
20 B3
19 NC
•
Random logic
•
Code converters
•
Fault detectors
•
Function generators
•
Address mapping
•
Multiplexing
I10 GND I11 B0 B1 B2
A = Plastic Leaded Chip Carrier
ORDERING INFORMATION
DESCRIPTION
24-Pin Plastic Dual In-Line 300mil-wide
28-Pin Plastic Leaded Chip Carrier
t
PD
(MAX)
10ns
10ns
ORDER CODE
PLUS173–10N
PLUS173–10A
DRAWING NUMBER
0410D
0401F
®PAL
is a registered trademark of Advanced Micro Devices Corporation.
October 22, 1993
41
853–1422 11164
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic array
(22
×
42
×
10)
PLUS173–10
LOGIC DIAGRAM
(LOGIC TERMS–P)
I0
I1
I2
I3
I4
I5
I6
I7
I8
1
2
3
4
5
6
7
8
9
(CONTROL TERMS)
I9 10
I10 11
I11 13
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
S9
X9
X8
X7
X6
X5
X4
X3
X2
X1
31
24 23
16 15
8 7
0
X0
S8
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
23 B9
22 B8
S7
21 B7
S6
20 B6
S5
19 B5
S4
18 B4
S3
17 B3
S2
16 B2
S1
15 B1
S0
14 B0
NOTES:
1. All programmed ‘AND’ gate locations are pulled to logic “1”.
2. All programmed ‘OR’ gate locations are pulled to logic “0”.
3.
Programmable connection.
October 22, 1993
42
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic array
(22
×
42
×
10)
PLUS173–10
FUNCTIONAL DIAGRAM
P31
I0
P0
D0
D9
I11
B0
B9
S9
X9
B9
S0
B0
X0
ABSOLUTE MAXIMUM RATINGS
1
RATING
SYMBOL
V
CC
V
IN
V
OUT
I
IN
I
OUT
T
amb
T
stg
PARAMETER
Supply voltage
Input voltage
Output voltage
Input currents
Output currents
Operating free-air temperature range
Storage temperature range
0
–65
–30
Min
Max
+7
+5.5
+5.5
+30
+100.0
+75
+150
UNIT
V
DC
V
DC
V
DC
mA
mA
°C
°C
THERMAL RATINGS
TEMPERATURE
Maximum junction
Maximum ambient
Allowable thermal rise
ambient to junction
150
°
C
75
°
C
75
°
C
NOTES:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those
indicated in the operational and programming specification of the device is not implied.
October 22, 1993
43
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic array
(22
×
42
×
10)
PLUS173–10
DC ELECTRICAL CHARACTERISTICS
0°C
≤
T
amb
≤
+75°C, 4.75
≤
V
CC
≤
5.25V
LIMITS
SYMBOL
Input voltage
2
V
IL
V
IH
V
IC
Low
High
Clamp
V
CC
= MIN
V
CC
= MAX
V
CC
= MIN, I
IN
= –12mA
2.0
–0.8
–1.2
0.8
V
V
V
PARAMETER
TEST CONDITIONS
MIN
TYP
1
MAX
UNIT
Output voltage
2
V
CC
= MIN
V
OL
V
OH
Low
4
High
5
I
OL
= 15mA
I
OH
= –2mA
2.4
0.4
2.9
0.5
V
V
Input current
9
V
CC
= MAX
I
IL
I
IH
Low
High
V
IN
= 0.45V
V
IN
= V
CC
–20
1
–100
40
µA
µA
Output current
V
CC
= MAX
I
O(OFF)
Hi-Z state
8
V
OUT
= 2.7V
V
OUT
= 0.45V
I
OS
I
CC
Capacitance
V
CC
= 5V
I
IN
C
B
Input
I/O
V
IN
= 2.0V
V
B
= 2.0V
8
15
pF
pF
Short circuit
3, 5, 6
V
CC
supply current
7
V
OUT
= 0V
V
CC
= MAX
–15
0
–15
–30
170
80
–140
–70
210
mA
mA
µA
NOTES:
1. All typical values are at V
CC
= 5V, T
amb
= +25°C.
2. All voltage values are with respect to network ground terminal.
3. Test one at a time.
4. Measured with inputs I0 – I4 = 0V, inputs I5 – I9 = 4.5V, I11 = 4.5V and I10 = 10V. For outputs B0 – B4 and for outputs B5 – B9 apply the
same conditions except I11 = 0V.
5. Same conditions as Note 4 except input I11 = +10V.
6. Duration of short circuit should not exceed 1 second.
7. I
CC
is measured with inputs I0 – I11 and B0 – B9 = 0V. Part in Virgin State.
8. Leakage values are a combination of input and output leakage.
9. I
IL
and I
IH
limits are for dedicated inputs only (I0 – I11).
October 22, 1993
44
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic array
(22
×
42
×
10)
PLUS173–10
AC ELECTRICAL CHARACTERISTICS
0°C
≤
T
amb
≤
+75°C, 4.75
≤
V
CC
≤
5.25V, R
1
= 300Ω, R
2
= 390Ω
TEST
SYMBOL
t
PD
t
OE
t
OD
PARAMETER
Propagation Delay
2
Output Enable
1
Output Disable
1
FROM
Input +/–
Input +/–
Input +/–
TO
Output +/–
Output –
Output +
CONDITION
C
L
= 30pF
C
L
= 30pF
C
L
= 5pF
MIN
LIMITS
TYP
8
8
8
MAX
10
10
10
UNIT
ns
ns
ns
NOTES:
1. For 3-State outputs; output enable times are tested with C
L
= 30pF to the 1.5V level, and S
1
is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with C
L
= 5pF. High-to-High impedance tests are made to an output
voltage of V
T
= (V
OH
– 0.5V) with S
1
open, and Low-to-High impedance tests are made to the V
T
= (V
OL
+ 0.5V) level with S
1
closed.
2. All propagation delays are measured and specified under worst case conditions.
VOLTAGE WAVEFORM
+3.0V
90%
TEST LOAD CIRCUIT
V
CC
+5V
S
1
10%
0V
5ns
+3.0V
90%
t
R
t
F
5ns
C
1
C
2
I
n
B
Z
R
1
INPUTS
I
n
B
M
DUT
R
2
C
L
10%
0V
5ns
5ns
B
M
GND
B
Z
OUTPUTS
MEASUREMENTS:
All circuit delays are measured at the +1.5V level
of inputs and outputs, unless otherwise specified.
NOTE:
C
1
and C
2
are to bypass V
CC
to GND.
Input Pulses
Test Load Circuit
TIMING DEFINITIONS
SYMBOL
t
PD
t
OD
PARAMETER
Propagation delay between
input and output.
Delay between input change
and when output is off (Hi-Z
or High).
Delay between input change
and when output reflects
specified output level.
TIMING DIAGRAM
+3V
I, B
1.5V
1.5V
1.5V
0V
V
OH
B
1.5V
V
T
t
OD
t
OE
1.5V
V
OL
t
PD
t
OE
October 22, 1993
45
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