PC7447A datasheet, PDF - EEWORLD Datasheet

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PC7447A: Description32-BIT, 1000 MHz, RISC PROCESSOR, CBGA360; Categorysemiconductor The embedded processor and controller; File Size596KB，44 Pages; ManufacturerAtmel (Microchip)

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PC7447A Overview

32-BIT, 1000 MHz, RISC PROCESSOR, CBGA360

PC7447A Parametric

Parameter Name	Attribute value
External data bus width	64
Number of terminals	360
Minimum operating temperature	-55 Cel
Maximum operating temperature	125 Cel
Line speed	1000 MHz
Processing package description	25 X 25 MM, 3.24 MM HEIGHT, 1.27 MM PITCH, CERAMIC, HITCE, BGA-360
state	Active
microprocessor_microcontroller_peripheral_ic_type	MICROPROCESSOR, RISC
Address bus width	36
Number of digits	32
boundary scan	YES
clock_frequency_max	167 MHz
form	FLOATING POINT
Integrated cache	YES
jesd_30_code	S-CBGA-B360
low power mode	YES
Packaging Materials	CERAMIC, METAL-SEALED COFIRED
ckage_code	BGA
packaging shape	SQUARE
Package Size	GRID ARRAY
qualification_status	COMMERCIAL
seated_height_max	3.2 mm
Rated supply voltage	1.1 V
Minimum supply voltage	1.05 V
Maximum supply voltage	1.15 V
surface mount	YES
Craftsmanship	CMOS
Temperature level	MILITARY
terminal coating	NOT SPECIFIED
Terminal form	BALL
Terminal spacing	1.27 mm
Terminal location	BOTTOM
length	25 mm
width	25 mm

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Features

•

3000 Dhrystone 2.1 MIPS at 1.3 GHz

Selectable Bus Clock (30 CPU Bus Dividers up to 28x)

Selectable MPx/60x Interface Voltage (1.8V, 2.5V)

Typically 18W at 1.33 GHz at V

= 1.3V; 8.0W at 1 GHz at V

= 1.1V

Full Operating Conditions

Nap, Doze and Sleep Power Saving Modes

Superscalar (Four Instructions Fetched Per Clock Cycle)

4 GB Direct Addressing Range

Virtual Memory: 4 Hexabytes (2

)

64-bit Data and 36-bit Address Bus Interface

Integrated L1: 32 KB Instruction and 32 KB Data Cache

Integrated L2: 512 KB

11 Independent Execution Units and 3 Register Files

Write-back and Write-through Operations

INT

Max = 1.33 GHz (1.42 GHz to be Confirmed)

BUS

Max = 133 MHz/166 MHz

PowerPC

7447A

RISC

Microprocessor

PC7447A

Preliminary

Description

The PC7447A host processor is a high-performance, low-power, 32-bit implementa-

tions of the PowerPC Reduced Instruction Set Computer (RISC) architecture

combined with a full 128-bit implementation of Freescale

’s AltiVec

™

technology.

This microprocessor is ideal for leading-edge embedded computing and signal pro-

cessing applications. The PC7447A features 512 KB of on-chip L2 cache. The

PC7447A microprocessor has no backside L3 cache, allowing for a smaller package

designed as a pin-for-pin replacement for the PC7447 microprocessor. This device

benefits from a silicon-on-insulator (SOI) CMOS process technology, engineered to

help deliver tremendous power savings without sacrificing speed. A low-power version

of the PC7447A microprocessor is also available.

Figure 1-1

shows a block diagram of the PC7447A. The core is a high-performance

superscalar design supporting a double-precision floating-point unit and a SIMD multi-

media unit. The memory storage subsystem supports the MPX bus protocol and a

subset of the 60x bus protocol to the main memory and other system resources.

Note that the PC7447A is a footprint-compatible, drop-in replacement in a PC7447

application if the core power supply is 1.3V.

Screening

•

Full Military Temperature Range (T

= -55°C, +125°C)

•

Industrial Temperature Range (T

= -40°C, +110°C)

GH suffix

HITCE 360

Rev. 5387B–HIREL–07/05

PC7447A [Preliminary]

Dedicated adder calculates effective addresses (EAs)

Supports store gathering

Performs alignment, normalization, and precision conversion for floating-point data

Executes cache control and TLB instructions

Performs alignment, zero padding, and sign extension for integer data

Supports hits under misses (multiple outstanding misses)

Supports both big- and little-endian modes, including misaligned little-endian

accesses

• Three issue queues, FIQ, VIQ, and GIQ, can accept as many as one, two, and three

instructions, respectively, in a cycle. Instruction dispatch requires the following:

– Instructions can only be dispatched from the three lowest IQ entries: IQ0, IQ1, and

IQ2

– A maximum of three instructions can be dispatched to the issue queues per clock

cycle

– Space must be available in the CQ for an instruction to dispatch (this includes

instructions that are assigned a space in the CQ but not in an issue queue)

• Rename buffers

– 16 GPR rename buffers

– 16 FPR rename buffers

– 16 VR rename buffers

• Dispatch unit

– Decode/dispatch stage fully decodes each instruction

• Completion unit

– The completion unit retires an instruction from the 16-entry completion queue (CQ)

when all instructions ahead of it have been completed, the instruction has finished

execution, and no exceptions are pending

– Guarantees sequential programming model (precise exception model)

– Monitors all dispatched instructions and retires them in order

– Tracks unresolved branches and flushes instructions after a mispredicted branch

– Retires as many as three instructions per clock cycle

• Separate on-chip L1 instruction and data caches (Harvard Architecture)

– 32-Kbyte, eight-way set-associative instruction and data caches

– Pseudo least-recently-used (PLRU) replacement algorithm

– 32-byte (eight-word) L1 cache block

– Physically indexed/physical tags

– Cache write-back or write-through operation programmable on a per-page or per-

block basis

5387B–HIREL–07/05

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