IS41C4100
IS41LV4100
1Meg x 4 (4-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
FEATURES
• TTL compatible inputs and outputs
• Refresh Interval: 1024 cycles/16 ms
• Refresh Mode :
RAS-Only, CAS-before-RAS
(CBR), and Hidden
• JEDEC standard pinout
• Single power supply
5V ± 10% (IS41C4100)
3.3V ± 10% (IS41LV4100)
• Industrail Temperature Range -40
o
C to 85
o
C
ISSI
DESCRIPTION
®
PRELIMINARY INFORMATION
SEPTEMBER 2001
The
ISSI
IS41C4100 and IS41LV4100 are 1,048,576 x 4-bit
high-performance CMOS Dynamic Random Access
Memory. Both products offer accelerated cycle access
EDO Page Mode. EDO Page Mode allows 512 random
accesses within a single row with access cycle time as
short as 10ns per 4-bit word.
These features make the IS41C4100 and IS41LV4100 ideally
suited for high band-width graphics, digital signal processing,
high-performance computing systems, and peripheral applications.
The IS41C4100 and IS41LV4100 are available in a 20-pin,
300-mil SOJ package.
KEY TIMING PARAMETERS
Parameter
Max.
RAS
Access Time (t
RAC
)
Max.
CAS
Access Time (t
CAC
)
Max. Column Address Access Time (t
AA
)
Min. Fast Page Mode Cycle Time (t
PC
)
Min. Read/Write Cycle Time (t
RC
)
-35
35
10
18
12
60
-60
60
15
30
25
110
Unit
ns
ns
ns
ns
ns
PIN CONFIGURATION
20-Pin SOJ
I/O0
I/O1
WE
RAS
A9
1
2
3
4
5
20
19
18
17
16
GND
I/O3
I/O2
CAS
OE
PIN DESCRIPTIONS
A0-A9
I/O0-I/O3
WE
OE
RAS
CAS
V
CC
GND
NC
Address Inputs
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Column Address Strobe
Power
Ground
No Connection
A0
A1
A2
A3
Vcc
6
7
8
9
10
15
14
13
12
11
A8
A7
A6
A5
A4
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the
best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
09/10/01
Rev. 00A
1
IS41C4100
IS41LV4100
Functional Description
The IS41C4100 and IS41LV4100 is a CMOS DRAM
optimized for high-speed bandwidth, low power applica-
tions. During READ or WRITE cycles, each bit is uniquely
addressed through the 19 address bits. The first ten
address bits (A0-A9) are entered as row address and
latter nine bits nine address bits (A0-A8) are entered as
column address. The row address is latched by the Row
Address Strobe (RAS). The column address is latched by
the Column Address Strobe (CAS).
RAS
is used to latch
the first nine bits and
CAS
is used the latter nine bits.
ISSI
®
2. Using a
CAS-before-RAS
refresh cycle.
CAS-before-
RAS
refresh is activated by the falling edge of
RAS,
while holding
CAS
LOW. In
CAS-before-RAS
refresh
cycle, an internal 10-bit counter provides the row
addresses and the external address inputs are ig-
nored.
CAS-before-RAS
is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Memory Cycle
A memory cycle is initiated by bring
RAS
LOW and it is
terminated by returning both
RAS
and
CAS
HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum t
RAS
time has expired. A new
cycle must not be initiated until the minimum precharge
time t
RP
, t
CP
has elapsed.
Extended Data Out Page Mode
EDO page mode operation permits all 512 columns within
a selected row to be randomly accessed at a high data
rate.
In EDO page mode read cycle, the data-out is held to the
next
CAS
cycle’s falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the
CAS
cycle time becomes shorter. There-
fore, in EDO page mode, the timing margin in read cycle
is larger than that of the fast page mode even if the
CAS
cycle time becomes shorter.
In EDO page mode, due to the extended data function, the
CAS
cycle time can be shorter than in the fast page mode
if the timing margin is the same.
The EDO page mode allows both read and write opera-
tions during one
RAS
cycle, but the performance is
equivalent to that of the fast page mode in that case.
Read Cycle
A read cycle is initiated by the falling edge of
CAS
or
OE,
whichever occurs last, while holding
WE
HIGH. The
column address must be held for a minimum time speci-
fied by t
AR
. Data Out becomes valid only when t
RAC
, t
AA
,
t
CAC
and t
OEA
are all satisfied. As a result, the access time
is dependent on the timing relationships between these
parameters.
Write Cycle
A write cycle is initiated by the falling edge of
CAS
and
WE,
whichever occurs last. The input data must be valid
at or before the falling edge of
CAS
or
WE,
whichever
occurs last.
Power-On
After application of the V
CC
supply, an initial pause of
200 µs is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS
signal).
During power-on, it is recommended that
RAS
track with
V
CC
or be held at a valid V
IH
to avoid current surges.
Refresh Cycle
To retain data, 1024 refresh cycles are required in each
16 ms period. There are two ways to refresh the memory.
1. By clocking each of the 1024 row addresses (A0
through A9) with
RAS
at least once every 16 ms. Any
read, write, read-modify-write or
RAS-only
cycle re-
freshes the addressed row.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00A
09/10/01
IS41C4100
IS41LV4100
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
T
V
CC
I
OUT
P
D
T
A
T
STG
Parameters
Voltage on Any Pin Relative to GND
Supply Voltage
Output Current
Power Dissipation
Commercial Operation Temperature
Industrail Temperature
Storage Temperature
5V
3.3V
5V
3.3V
Rating
–1.0 to +7.0
-0.5 to 4.6
–1.0 to +7.0
-0.5 to 4.6
50
1
0 to +70
–40 to +85
–55 to +125
Unit
V
V
V
V
mA
W
°C
°C
°C
ISSI
®
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltages are referenced to GND.)
Symbol
V
CC
V
IH
V
IL
T
A
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Commercial Ambient Temperature
Industrail Ambient Temperature
5V
3.3V
5V
3.3V
5V
3.3V
Min.
4.5
3.0
2.4
2.0
–1.0
–0.3
0
–40
Typ.
5.0
3.3
—
—
—
—
—
—
Max.
5.5
3.6
V
CC
+ 1.0
V
CC
+ 0.3
0.8
0.8
70
85
Unit
V
V
V
°C
°C
CAPACITANCE
(1,2)
Symbol
C
IN
1
C
IN
2
C
IO
Parameter
Input Capacitance: A0-A9
Input Capacitance:
RAS, CAS, WE, OE
Data Input/Output Capacitance: I/O0-I/O3
Max.
5
7
7
Unit
pF
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25°C, f = 1 MHz,
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
09/10/01
Rev. 00A
5
PCB Design
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