2. Operating Temperature Range: S (-10℃~60℃), C(0℃~70℃), E(-25℃~85℃), I (-40℃~85℃)
CMOS LPRAM
Function
48-FBGA, 60ns, V
CC
=3.0V, V
CCQ
=3.0V(2.5V,1.8V)
48-FBGA, 70ns, V
CC
=3.0V, V
CCQ
=3.0V(2.5V,1.8V)
FUNCTIONAL DESCRIPTION
/CS
H
X
1)
H
X
1)
L
H
H
H
X
1)
L
L
L
H
L
X
1)
L
H
L
1. X means don’t care.(Must be low or high state)
2. In case of FMP3217CA2 & FMP3217CA5 fproduct
3. In case of FMP3217CA1 & FMP3217CA4 product
/ZZ
H
L
L
H
H
/OE
X
1)
X
1)
X
1)
X
1)
H
/WE
X
1)
X
1)
X
1)
X
1)
H
/LB
X
1)
X
1)
X
1)
H
L
/UB
X
1)
X
1)
X
1)
H
X
1)
L
H
L
L
H
L
L
I/O1-8
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
High-Z
Dout
Din
High-Z
Din
I/O9-16
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
Dout
High-Z
Din
Din
Mode
Deselected
Deselected
Deselected
Deselected
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
Lower Byte Write
Upper Byte Write
Word Write
Power
Standby
Direct DPD
2)
Low Power Modes
3)
Standby
Active
Active
Active
Active
Active
Active
Active
Active
H
H
L
ABSOLUTE MAXIMUM RATINGS
1)
Item
Voltage on any pin relative to V
SS
Voltage on V
CC
supply relative to V
SS
Power Dissipation
Storage temperature
Symbol
V
IN
, V
OUT
V
CC
P
D
T
STG
Ratings
-0.5 to V
CC
+0.3V
-0.2 to 3.6
1.0
-55 to 150
Unit
V
V
W
℃
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation should be restricted to
recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
FMP3217CA
Item
Supply voltage
I/O operating voltage (V
CCQ
≤
V
CC
)
Ground
Input high voltage
Input low voltage
Note :
1. Overshoot : Vcc+1.0V in case of pulse width≤20ns.
2. Undershoot : -1.0V in case of pulse width≤20ns.
3. Overshoot and undershoot are sampled, not 100% tested.
Symbol
Min
V
CC
V
CCQ
V
SS
V
IH
V
IL
2.7
1.7
0
V
CC
– 0.4V
-0.2
2)
Typ
3.0V
3.0V
0
V
CC
0
Max
3.3
3.3
0
V
CC
+0.2
1)
0.4V
Unit
V
V
V
V
V
3
Revision 0.0
Oct. 2007
FMP3217CAx
CAPACITANCE
1)
Item
Input capacitance
Input/Output capacitance
1. Capacitance is sampled, not 100% tested.
CMOS LPRAM
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
2
3.5
Max
6.5
6.5
Unit
pF
pF
(f=1MHz , T
A
=25℃)
DC AND OPERATING CHARACTERISTICS
Item
Input leakage current
Output leakage current
Symbol
I
LI
I
LO
I
CC1
Average operating current
I
CC2
Output low voltage
Output high voltage
Standby Current(TTL)
Standby Current(CMOS)
V
OL
V
OH
I
SB
I
SB1
I
SB0
Low Power Modes
I
SB0a
I
SB0b
I
SB0c
V
IN
=V
SS
to V
CC
/CS=V
IH
, /ZZ=V
IH
, /OE=V
IH
or /WE=V
IL
, V
IO
=V
SS
to V
CC
Cycle time=1us, 100%duty, I
IO
=0mA, /CS≤0.2V, /ZZ=V
IH
,
V
IN
≤0.2V
or V
IN
≥V
CC
-0.2V
Cycle time=Min, I
IO
=0mA, 100% duty, /CS=V
IL
, /ZZ=V
IH
,
V
IN
=V
IL
or V
IH
I
OL
=0.5mA
I
OH
=-0.5mA
/CS=V
IH
, /ZZ=V
IH
, Other inputs=V
IH
or V
IL
/CS≥V
CC
-0.2V, /ZZ≥V
CC
-0.2V, Other inputs=0~V
CC
/ZZ≤0.2V, Other inputs=0~V
CC
, No refresh(DPD)
/ZZ≤0.2V, Other inputs=0~V
CC
, ¼ refresh area selection
/ZZ≤0.2V, Other inputs=0~V
CC
, ½ refresh area selection
/ZZ≤0.2V, Other inputs=0~V
CC
, All refresh area selection
0.8VCCQ
-
-
-
-
-
-
-
-
-
-
-
-
0.3
120
10
90
100
120
Test Conditions
Min
-1
-1
-
-
Typ
-
-
-
-
Max
1
1
3
20
0.2VCCQ
Unit
uA
uA
mA
mA
V
V
mA
uA
uA
uA
uA
uA
Operating Range
Device
FMP3217CAx-XxxS
FMP3217CAx-XxxC
FMP3217CAx-XxxE
FMP3217CAx-XxxI
Range
Special
Commercial
Extended
Industrial
Ambient Temperature
-10℃ to +60℃
0℃ to +70℃
2.7V to 3.3V
-25℃ to +85℃
-40℃ to +85℃
1.7V to V
cc
V
CC
V
CCQ
4
Revision 0.0
Oct. 2007
FMP3217CAx
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Input/Output Reference)
Input pulse level : 0.2 to VCC-0.2V
Input rising and falling time : 5ns
Input and output reference voltage : 0.5*VCCQ
Output load(see right) : C
L
=30pF+1TTL
30pf
CMOS LPRAM
1TTL
AC CHARACTERISTICS
(V
CC
=2.7V~3.3V)
Speed Bins
Parameter List
Symbol
Min
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
/UB, /LB Access Time
Chip Select to Low-Z Output
Read
/UB, /LB Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High- Z Output
/UB, /LB Disable to High- Z Output
Output Disable to High- Z Output
Output Hold from Address Change
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
/UB, /LB Valid to End of Write
Write
Write Pulse Width
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
Page Mode Cycle Time
Page
Page Mode Address Access Time
Maximum Cycle Time
/CS High Pulse Width
tRC
tAA
tCO
tOE
tBA
tLZ
tBLZ
tOLZ
tHZ
tBHZ
tOHZ
tOH
tWC
tCW
tAS
tAW
tBW
tWP
tWR
tWHZ
tDW
tDH
tOW
tPC
tPAA
tMRC
tCP
60
-
-
-
-
10
10
3
0
0
0
5
60
50
0
50
50
50
0
0
20
0
5
20
-
-
10
60ns
Max
20k
60
60
20
60
-
-
-
8
8
8
-
20k
-
-
-
-
-
-
8
-
-
-
-
20
20k
-
Min
70
-
-
-
-
10
10
3
0
0
0
5
70
60
0
60
60
50
0
0
20
0
5
20
-
-
10
70ns
Max
20k
70
70
20
70
-
-
-
8
8
8
-
20k
-
-
-
-
-
-
8
-
-
-
-
25
20k
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
1. /CS High Pulse Width is defined by /CS or (/UB and /LB) because /UB & /LB can make standby mode when /UB=High and /LB=High.
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FPGA/CPLD
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