ZL30105QDG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Wireless rf/communication> Telecom circuit> ZL30105QDG

ZL30105QDG: DescriptionSPECIALTY TELECOM CIRCUIT, PQFP64; CategoryWireless rf/communication Telecom circuit; File Size473KB，52 Pages; ManufacturerZarlink Semiconductor (Microsemi); Websitehttp://www.zarlink.com/

Download Datasheet Parametric Compare View All

ZL30105QDG Overview

SPECIALTY TELECOM CIRCUIT, PQFP64

ZL30105QDG Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
package instruction	TFQFP, TQFP64,.47SQ
Reach Compliance Code	compli
JESD-30 code	S-PQFP-G64
JESD-609 code	e0
length	10 mm
Humidity sensitivity level	3
Number of functions	1
Number of terminals	64
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TFQFP
Encapsulate equivalent code	TQFP64,.47SQ
Package shape	SQUARE
Package form	FLATPACK, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	240
power supply	1.8,3.3 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Telecom integrated circuit types	TELECOM CIRCUIT
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	10 mm
Base Number Matches	1

Preview

Download Datasheet

View All

ZL30105

T1/E1/SDH Stratum 3 Redundant System Clock

Synchronizer for AdvancedTCA™ and H.110

Data Sheet

Features

•

Synchronizes to clock-and-sync-pair to maintain

minimal phase skew between the master-clock

and the redundant slave-clock

Supports ITU-T G.813 option 1, G.823 for

2048 kbit/s and G.824 for 1544 kbit/s interfaces

Supports Telcordia GR-1244-CORE Stratum

3/4/4E

Supports ANSI T1.403 and ETSI ETS 300 011 for

ISDN primary rate interfaces

Accepts three input references and synchronizes

to any combination of 2 kHz, 8 kHz, 1.544 MHz,

2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz

inputs

Provides a range of clock outputs: 1.544 MHz

(DS1), 2.048 MHz (E1), 3.088 MHz, 16.384 MHz,

and 19.44 MHz (SDH), and either 4.096 MHz and

8.192 MHz or 32.768 MHz and 65.536 MHz, and a

choice of 6.312 MHz (DS2), 8.448 MHz (E2),

44.736 MHz (DS3) or 34.368 MHz (E3)

Provides 5 styles of 8 kHz framing pulses and a

2 kHz multi-frame pulse

Holdover frequency accuracy of 1x10

-8

Selectable loop filter 1.8 Hz, 3.6 Hz or 922 Hz

Less than 24 ps

rms

intrinsic jitter on the 19.44 MHz

output clock, compliant with GR-253-CORE OC-3

and G.813 STM-1 specifications

OSCi

OSCo

TIE_CLR

November 2005

Ordering Information

ZL30105QDG

ZL30105QDG1

64 pin TQFP Trays

64 pin TQFP* Trays Bake & Drypack

* Pb Free Matte Tin

•

-40°C to +85°C

•

Less than 0.6 ns

intrinsic jitter on all output

clocks and frame pulses

Manual or Automatic hitless reference switching

between any combination of valid input reference

frequencies

Provides Lock, Holdover and selectable Out of

Range indication

Simple hardware control interface

Selectable external master clock source: Clock

Oscillator or Crystal

•

Applications

•

Synchronization and timing control for multi-trunk

SDH and T1/E1 systems such as DSLAMs,

Gateways and PBXs

Clock and frame pulse source for

AdvancedTCA™- and other time division

multiplex (TDM) buses

LOCK

OUT_SEL2

•

FASTLOCK

Master Clock

REF0

REF1

REF2

REF2_SYNC

REF_FAIL0

REF_FAIL1

REF_FAIL2

REF_SEL1:0

RST

State Machine

Reference

Monitor

TIE

Corrector

Enable

Mode

Control

MUX

TIE

Corrector

Circuit

Virtual

Reference

DPLL

Synthesizer

DS1

Synthesizer

SDH

Synthesizer

Programmable

Synthesizer

IEEE

1149.1a

TCK

TDI TMS TDO

Frequency

Select

MUX

C2o

C4/C65o

C8/C32o

C16o

F4/F65o

F8/F32o

F16o

C1.5o

C3o

C19o

F2ko

C6/8.4/34/44o

OUT_SEL1:0

TRST

MODE_SEL1:0

HMS

HOLDOVER

SEC_MSTR

APP_SEL1:0

Figure 1 - Functional Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

ZL30105

Table of Contents

Data Sheet

1.0 Change Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.0 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1 Reference Select Multiplexer (MUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.2 Reference Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.3 Time Interval Error (TIE) Corrector Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.4 Digital Phase Lock Loop (DPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.5 Frequency Synthesizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.6 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.7 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.0 Control and Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1 Application Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.2 Loop Filter and Limiter Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.3 Output Clock and Frame Pulse Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.4.1 Freerun Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.4.2 Holdover Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.4.3 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.4.4 Automatic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.5 Reference Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.5.1 Manual Reference Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.5.2 Automatic Reference Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.5.2.1 Automatic Reference Switching - Coarse Reference Failure . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.5.2.2 Automatic Reference Switching - Reference Frequency Out-of-Range . . . . . . . . . . . . . . . . . 26

4.6 Clock Redundancy Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.0 Measures of Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.1 Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.2 Jitter Generation (Intrinsic Jitter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.3 Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.4 Jitter Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.5 Frequency Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.6 Holdover Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.7 Pull-in Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.8 Lock Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.9 Phase Slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.10 Time Interval Error (TIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.11 Maximum Time Interval Error (MTIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.12 Phase Continuity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.13 Lock Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.1 Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.2 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.2.1 Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.2.2 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.3 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.4 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.5 Clock Redundancy System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.0 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.1 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Zarlink Semiconductor Inc.

ZL30105

List of Figures

Data Sheet

Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2 - Pin Connections (64 pin TQFP, please see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3 - Reference Monitor Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 4 - Behaviour of the Dis/Re-qualify Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 5 - DS1 Out-of-Range Thresholds for APP_SEL1:0=00. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 6 - E1 Out-of-Range Thresholds for APP_SEL=01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 7 - Out-of-Range Thresholds for APP_SEL=10 and APP_SEL=11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 8 - REF2_SYNC Reference Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 9 - Timing Diagram of Hitless Reference Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 10 - Timing Diagram of Hitless Mode Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 11 - DPLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 12 - Mode Switching in Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 13 - Reference Switching in Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 14 - Reference Selection in Automatic Mode (MODE_SEL=11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 15 - Mode Switching in Automatic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 16 - Automatic Reference Switching - Coarse Reference Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 17 - Automatic Reference Switching - Out-of-Range Reference Failure . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 18 - Examples of REF2 & REF2_SYNC to Output Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 19 - Clock Redundancy with Two Independent Timing Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 20 - Clock Oscillator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 21 - Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 22 - Power-Up Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 23 - Typical Clocking Architecture of an ECTF H.110 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 24 - Typical Clocking Architecture of a PICMG AdvancedTCA™ System . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 25 - Timing Parameter Measurement Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 26 - REF0/1/2 Input Timing and Input to Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 27 - REF2_SYNC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 28 - E1 Output Timing Referenced to F8/F32o. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 29 - DS1 Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 30 - SDH Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 31 - DS3, E3, E2 and DS2 Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Zarlink Semiconductor Inc.

ZL30105QDG Related Products

	ZL30105QDG	ZL30105QDG1	ZL30105_05
Description	SPECIALTY TELECOM CIRCUIT, PQFP64	SPECIALTY TELECOM CIRCUIT, PQFP64	SPECIALTY TELECOM CIRCUIT, PQFP64
Number of functions	1	1	1
Number of terminals	64	64	64
Maximum operating temperature	85 °C	85 °C	85 Cel
Minimum operating temperature	-40 °C	-40 °C	-40 Cel
surface mount	YES	YES	Yes
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	GULL WING	GULL WING	GULL WING
Terminal location	QUAD	QUAD	QUAD
Is it Rohs certified?	incompatible	conform to	-
package instruction	TFQFP, TQFP64,.47SQ	TFQFP,	-
Reach Compliance Code	compli	compli	-
JESD-30 code	S-PQFP-G64	S-PQFP-G64	-
length	10 mm	10 mm	-
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	-
encapsulated code	TFQFP	TFQFP	-
Package shape	SQUARE	SQUARE	-
Package form	FLATPACK, THIN PROFILE, FINE PITCH	FLATPACK, THIN PROFILE, FINE PITCH	-
Peak Reflow Temperature (Celsius)	240	NOT SPECIFIED	-
Certification status	Not Qualified	Not Qualified	-
Maximum seat height	1.2 mm	1.2 mm	-
Nominal supply voltage	1.8 V	1.8 V	-
Telecom integrated circuit types	TELECOM CIRCUIT	TELECOM CIRCUIT	-
Terminal pitch	0.5 mm	0.5 mm	-
Maximum time at peak reflow temperature	30	NOT SPECIFIED	-
width	10 mm	10 mm	-
Base Number Matches	1	1	-

Recommended Resources

Bipolar long-distance measurement signal forwarding circuit

Dual power supply voltage regulator circuit diagram

KTM03 zero-crossing trigger power regulator circuit

Application of Huifeng frequency converter in refrigeration equipment

555 water-saving infrared automatic switch faucet circuit

Ultra shortwave tuner circuit with M0S prestage

Here is a trick to keep a public parking space always available for you.: Nowadays, cars are everywhere. If there is no dedicated parking space, many friends dare not drive out at night. Why? Parking space is tight! If you come back late, you can only leave your car on the ...; xyh_521 Creative Market

What do horizontal wiring and vertical wiring specifically refer to?: Is it a wiring method? Is it done manually or by setting "rules"?...; 44444444444444 PCB Design

In power-off mode, the circuit board is stationary and the lithium battery runs out of power: The old circuit board has a microcontroller operating voltage of about 3v~3.6v. Due to a mistake, the circuit board was made to be powered directly by a lithium battery. The lithium battery is fully c...; 545934451 MCU

2014 Top 10 Disruptive Technologies 3D Micro-Printers: According to a report on the Spanish newspaper El Mundo on May 1, MIT has always been known for its leading scientific and technological innovation capabilities. Its MIT Technology Review magazine con...; azhiking Energy Infrastructure?

Urgent! Urgent! How to set the timer clock of ep9315? ? ?: How do I set the timer clock of ep9315? I have searched the entire user guide but couldn't find it. If anyone knows, please let me know! Thanks a lot!...; zhiweihappy Embedded System

Looking for loyal fans of NI Labview and giving them a NI customized backpack!: Another thing I got at NIDAYs was a NI customized Lexon backpack. I decided to do it as a favor and give it to NI Labview fans! A quick check online revealed that the backpack is made in France. Weari...; EEWORLD社区 Test/Measurement

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components