PGA2500
SBOS289A − NOVEMBER 2003 − REVISED DECEMBER 2003
Digitally Controlled
Microphone Preamplifier
FEATURES
D
Fully Differential Input-to-Output Architecture
D
Digitally Controlled Gain Using Serial Port
Interface:
− Gain Range: 10dB through 65dB, 1dB per
step
− Unity (0dB) Gain Setting via Serial Port or
Dedicated Control Pin
Dynamic Performance:
− Equivalent Input Noise with Z
S
= 150Ω and
Gain = 30dB: −128dBu
− Total Harmonic Distortion plus Noise
(THD+N) with Gain = 30dB: 0.0004%
Zero Crossing Detection Minimizes Audible
Artifacts when Gain Switching
Integrated DC Servo Minimizes Output Offset
Voltage
Common-Mode Servo Improves CMRR
Four-Wire Serial Control Port Interface:
− Simple Interface to Microprocessor or
DSP Serial Ports
− Supports Daisy-Chaining of Multiple
PGA2500 Devices
Dedicated Input Pin for Selecting Unity Gain
Overload Output Pin Provides Clipping
Indication
Four General-Purpose Digital Output Pins
Requires
±5V
Power Supplies
Available in an SSOP-28 Package
APPLICATIONS
D
Microphone Preamplifiers and Mixers
D
Digital Mixers and Recorders
DESCRIPTION
The PGA2500 is a digitally controlled, analog microphone
preamplifier designed for use as a front end for high-
performance audio analog-to-digital converters (ADCs). The
PGA2500 features include low noise, wide dynamic range,
and a differential signal path. An on-chip DC servo loop is
employed to minimize DC offset, while a common-mode
servo function may be used to enhance common-mode
rejection.
The PGA2500 features a gain range of 10dB through 65dB
(1dB/step), along with a unity gain setting. The wide gain
range allows the PGA2500 to be used with a variety of
microphones. Gain settings and internal functions are
programmed using a 16-bit control word, which is loaded
using a simple serial port interface. A serial data output pin
provides support for daisy-chained connection of multiple
PGA2500 devices. Four programmable digital outputs are
provided for controlling the external switching of input pads,
phantom power, high pass filters, and polarity reversal
functions. The PGA2500 requires both +5V and −5V power
supplies and is available in a small SSOP-28 package.
D
D
D
D
D
D
D
D
D
D
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright
2003, Texas Instruments Incorporated
www.ti.com
PGA2500
www.ti.com
SBOS289A − NOVEMBER 2003 − REVISED DECEMBER 2003
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range unless otherwise noted(1)
PGA2500
Supply Voltage, VA+
Supply Voltage, VA−
Supply Voltage, VD−
Voltage Difference, VA− to VD−
Analog input voltage
Digital input voltage
Operating Temperature Range
+5.5
−5.5
−5.5
Less than 300
(VA−) −0.3 to (VA+) +0.3
−0.3 to (VA+) + 0.3
−40 to +85
UNIT
V
V
V
mV
V
V
°C
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
Storage Temperature Range
−60 to +150
°C
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
ORDERING INFORMATION
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR(1)
DB
SPECIFIED
TEMPERATURE
RANGE
−40 C +85 C
−40°C to +85°C
PACKAGE
MARKING
PGA2500I
ORDERING
NUMBER
PGA2500IDB
PGA2500IDBR
TRANSPORT
MEDIA, QUANTITY
Rails, 48
Tape and Reel, 1000
PGA2500
SSOP-28
(1) For the most current specifications and package information, refer to our web site at www.ti.com.
2
PGA2500
www.ti.com
SBOS289A − NOVEMBER 2003 − REVISED DECEMBER 2003
ELECTRICAL CHARACTERISTICS
All parameters specified with T
A
= +25°C, VA+ = +5V, VA− = −5V, VD− = −5V, and V
COM
IN = 0V, unless otherwise noted
.
PGA2500
PARAMETER
DC Characteristics
Step Size
Gain Error
AC Characteristics
THD+N with f
IN
= 1kHz
Analog Input
Maximum Input Voltage
Input Resistance
Per Input Pin
Differential
Analog Output
Output Voltage Range
Output Offset Voltage
Input Referred Offset
Output Resistive Loading
Load Capacitance Stability
Short Circuit Current
Digital Characteristics
High-Level Input Voltage, V
IH
Low-Level Input Voltage, V
IL
High-Level Output Voltage, V
OH
Low-Level Output Voltage, V
OL
Input Leakage Current, I
IN
Switching Characteristics
Serial Clock (SCLK) Frequency
Serial Clock (SCLK) Pulse Width Low
Serial Clock (SCLK) Pulse Width High
Input Timing
SDI Setup Time
SDI Hold Time
CS Falling to SCLK Rising
SCLK Falling to CS Rising
Output Timing
CS Low to SDO Active
SCLK Falling to SDO Data Valid
CS High to SDO High Impedance
Power Supply
Operating Voltage
VA+
VA−
VD−
Quiescent Current
IA+
IA−
ID−
VA+ = +5V
VA− = −5V
VD− = −5V
30
30
1
40
40
2
mA
mA
mA
+4.75
−4.75
−4.75
+5
−5
−5
+5.25
−5.25
−5.25
V
V
V
t
CSO
t
CFDO
t
CSZ
35
60
100
ns
ns
ns
t
SDS
t
SDH
t
CSCR
t
CFCS
20
20
90
35
ns
ns
ns
ns
f
SCLK
t
PH
t
PL
0
80
80
10-second duration
+2.0
−0.3
(VA+) − 1.0
2
V
COM
IN = 0V, R
L
= 600Ω
DC Servo On, Any Gain
DC Servo Off, Gain = 30dB
VA− +0.9
±0.04
±1
600
100
100
VA+
0.8
0.4
10
6.25
VA+ −0.9
±1
V
mV
mV
Ω
pF
mA
V
V
V
V
µA
MHz
ns
ns
Gain = 0dB, V
OUT
= 3.5V
RMS
, V
COM
IN = 0V
Gain = 30dB, V
OUT
= 3.5V
RMS
, V
COM
IN = 0V
Gain = 0dB
VA− +1.5
4600
9200
−114
−108
−108
−102
VA+ −2.0
dB
dB
V
Ω
Ω
TEST CONDITIONS
MIN
TYP
1
0.5
MAX
UNIT
Gain = 10dB through 65dB
All Gain Settings
dB
dB
I
O
= 200µA
I
O
= −3.2mA
3
PGA2500
www.ti.com
SBOS289A − NOVEMBER 2003 − REVISED DECEMBER 2003
PIN CONFIGURATION
GPO1
GPO2
GPO3
GPO4
OVR
DGND
DCEN
0dB
ZCEN
SDI
CS
SCLK
SDO
VD
−
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PGA2500
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AGND
V
IN
+
V
IN
−
V
COM
IN
C
S1 1
C
S1 2
C
S2 1
C
S2 2
VA
−
VA+
VA+
V
OUT
+
V
OUT
−
VA
−
PIN DESCRIPTIONS
PIN NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
4
NAME
GPO1
GPO2
GPO3
GPO4
OVR
DGND
DCEN
0dB
ZCEN
SDI
CS
SCLK
SDO
VD−
VA−
V
OUT
−
V
OUT
+
VA+
VA+
VA−
C
S22
C
S21
C
S12
C
S11
V
COM
IN
V
IN
−
V
IN
+
AGND
DESCRIPTION
General-Purpose CMOS Logic Output
General-Purpose CMOS Logic Output
General-Purpose CMOS Logic Output
General-Purpose CMOS Logic Output
Over Range Output (Active High)
Digital Ground
DC Servo Enable (Active Low)
Unity Gain Enable (Active High)
Zero Crossing Detector Enable (Active High)
Serial Data Input
Chip Select Input (Active Low)
Serial Data Clock Input
Serial Data Output
−5V Digital Supply
−5V Analog Supply
Analog Output, Inverting
Analog Output, Non-Inverting
+5V Analog Supply
+5V Analog Supply
−5V Analog Supply
DC Servo Capacitor #2, Terminal 2
DC Servo Capacitor #2, Terminal 1
DC Servo Capacitor #1, Terminal 2
DC Servo Capacitor #1, Terminal 1
Common Mode Voltage Input, 0V to +2.5V
Analog Input, Inverting
Analog Input, Noninverting
Analog Ground
PGA2500
www.ti.com
SBOS289A − NOVEMBER 2003 − REVISED DECEMBER 2003
TYPICAL CHARACTERISTICS
All specifications at T
A
= +25°C, VA+ = +5V, VA− = −5V, VD− = −5V, and V
COM
IN = 0V, unless otherwise noted.
EQUIVALENT INPUT NOISE (E.I.N.) AS A FUNCTION OF GAIN
(with Z = 0Ω)
−100
−
102
−104
−106
−
108
−110
−112
−114
−
116
−118
−120
−
122
−124
−126
−128
−
130
−132
−134
−136
10 15 20 25 30 35 40 45 50 55 60 65
Gain (dB)
EQUIVALENT INPUT NOISE (E.I.N.) AS A FUNCTION OF GAIN
(with Z = 150Ω)
−100
−102
−104
−106
−108
−110
−112
−114
−116
−118
−120
−122
−124
−126
−128
−130
10 15 20 25 30 35 40 45 50 55 60 65
Gain (dB)
E.I.N. (dBu)
THD+N vs GAIN
(with 4.0 V
RMS
Output and Z = 40Ω)
0.01
E.I.N. (dBu)
−80
−85
THD+N and Noise (dB)
−90
−95
−100
−105
−110
−115
−120
−125
−130
THD+N AND NOISE vs GAIN
(0dB = 4V
RMS
)
THD+N
with Z = 40Ω
THD+N (%)
0.001
Noise
with Z = 0Ω
0.0001
10
15
20
25
30
35 40 45
Gain (dB)
50
55
60
65
10
15
20
25
30
35 40 45
Gain Set (dB)
50
55
60
65
THD+N vs FREQUENCY
(R
S
= 40Ω, R
L
= 600Ω, V
COM
IN = 0V, BW = 22Hz to 22kHz)
0.1
V
OUT
= 4.0Vrms Differential
for Gains = 10, 20, 30, 40, 50, and 60dB
V
OUT
= 3.5Vrms Differential for Gain = 0dB
THD+N Ratio (%)
0.01
60dB
50dB
40dB
30dB
10dB
0dB
0.0001
20
100
1k
Frequency (Hz)
10k
20k
20dB
0.0001
THD+N Ratio (%)
0.01
0.1
THD+N vs FREQUENCY
(R
S
= 40Ω, R
L
= 600Ω, V
COM
IN = +2.5V, BW = 22Hz to 22kHz)
V
OUT
= 2.0Vrms Differential
for Gains = 10, 20, 30, 40, 50, and 60dB
V
OUT
= 1.0Vrms Differential for Gain = 0dB
60dB
50dB
0.001
0dB
40dB
10dB
0.001
30dB
20dB
20
100
1k
Frequency (Hz)
10k
20k
5
Embedded System
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