ZL30111
POTS Line Card PLL
Data Sheet
Features
•
•
•
•
•
•
•
•
•
Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or
19.44 MHz input
Provides a range of clock outputs: 2.048 MHz,
4.096 MHz and 8.192 MHz
Provides 2 styles of 8 kHz framing pulses
Automatic entry and exit from freerun mode on
reference fail
Provides DPLL lock and reference fail indication
DPLL bandwidth of 922 Hz for all rates of input
reference and 58 Hz for an 8 kHz input reference
Less than 0.6 ns
pp
intrinsic jitter on all output clocks
20 MHz external master clock source: clock
oscillator or crystal
Simple hardware control interface
Ordering Information
ZL30111QDG
ZL30111QDG1
64 Pin TQFP Trays, Bake & Drypack
64 Pin TQFP* Trays, Bake & Drypack
*Pb Free Matte Tin
-40°C to +85°C
January 2007
Applications
•
•
Synchronizer for POTS line cards
Rate convert NTR 8kHz or GPON physical
interface clock to TDM clock
Description
The ZL30111 POTS line card PLL contains a digital
phase-locked loop (DPLL), which provides timing and
synchronization for SLIC/CODEC devices.
The ZL30111 generates TDM clock and framing
signals that are phase locked to the input reference.
It helps ensure system reliability by monitoring its
reference for stability and by maintaining stable
output clocks during short periods when the
reference is unavailable.
REF_FAIL
LOCK
REF
DPLL
Reference
Monitor
Mode
Control
C2o
C4
C8
F4
F8
RST
OSCi
OSCo
State Machine
Master
Clock
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2007, Zarlink Semiconductor Inc. All Rights Reserved.
ZL30111
Table of Contents
Data Sheet
1.0 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Reference Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Digital Phase Lock Loop (DPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Frequency Synthesizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.0 DPLL Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Freerun Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.0 Measures of Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 Jitter Generation (Intrinsic Jitter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3 Jitter Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4 Lock Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1 Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.2 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.2.1 Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.2.2 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.4 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.0 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.2 Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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Zarlink Semiconductor Inc.
ZL30111
List of Figures
Data Sheet
Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - Pin Connections (64 pin TQFP, please see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3 - Reference Monitor Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4 - DPLL Mode Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5 - Clock Oscillator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6 - Power-Up Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7 - Timing Parameter Measurement Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8 - Input to Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9 - Output Timing Referenced to F8o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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Zarlink Semiconductor Inc.
ZL30111
1.0
1.1
Data Sheet
Physical Description
Pin Connections
F4/F65o
IC
AGND
IC
IC
NC
REF0
NC
IC
NC
IC
IC
V
DD
NC
IC
IC
F8/F32o
IC
C2o
AV
DD
AV
DD
C8/C32o
C4/C65o
AGND
AGND
NC
NC
AV
DD
AV
DD
AV
CORE
AGND
AGND
48
50
30
52
28
54
56
58
22
60
20
62
18
64
2
4
6
8
10
12
14
16
26
24
46
44
42
40
38
36
34
32
ZL30111
IC
NC
NC
AV
DD
IC
IC
IC
V
DD
NC
GND
IC
OSCi
OSCo
RST
IC
IC
Figure 2 - Pin Connections (64 pin TQFP, please see Note 1)
Note 1: The ZL30111 uses the TQFP shown in the package outline designated with the suffix QD, the ZL30111
does not use the e-Pad TQFP.
V
CORE
LOCK
REF_FAIL
IC
IC
IC
IC
IC
IC
IC
V
CORE
GND
AV
CORE
IC
IC
GND
4
Zarlink Semiconductor Inc.
ZL30111
1.2
Pin Description
Pin Description
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Name
GND
V
CORE
LOCK
REF_FAIL
IC
IC
IC
IC
IC
IC
IC
V
CORE
GND
AV
CORE
IC
IC
IC
IC
RST
Ground.
0 V.
Positive Supply Voltage.
+1.8 V
DC
nominal.
Description
Data Sheet
Lock Indicator (Output).
This output goes to a logic high when the PLL is frequency
locked to the selected input reference.
Reference Failure Indicator (Output).
A logic high at this pin indicates that the REF
reference frequency is exhibiting abrupt phase or frequency changes.
Internal Connection.
Leave unconnected.
Internal Connection.
Leave unconnected.
Internal Connection.
Leave unconnected.
Internal Connection.
Leave unconnected.
Internal Connection.
Leave unconnected.
Internal Connection.
Connect to GND.
Internal Connection.
Connect to GND.
Positive Supply Voltage.
+1.8 V
DC
nominal.
Ground.
0 V.
Positive Analog Supply Voltage.
+1.8 V
DC
nominal.
Internal Connection.
Leave unconnected.
Internal Connection.
Connect to VDD.
Internal Connection.
Connect to GND.
Internal Connection.
Connect to GND.
Reset (Input).
A logic low at this input resets the device. On power up, the RST pin
must be held low for a minimum of 300 ns after the power supply pins have reached
the minimum supply voltage. When the RST pin goes high, the device will transition
into a Reset state for 3 ms. In the Reset state all clock and frame pulse outputs will be
forced into high impedance.
Oscillator Master Clock (Output).
For crystal operation, a 20 MHz crystal is connected
from this pin to OSCi. This output is not suitable for driving other devices. For clock
oscillator operation, this pin must be left unconnected.
Oscillator Master Clock (Input).
For crystal operation, a 20 MHz crystal is connected
from this pin to OSCo. For clock oscillator operation, this pin must be connected to a
clock source.
Internal Connection.
Leave unconnected.
Ground.
0 V.
No internal bonding Connection.
Leave unconnected.
Positive Supply Voltage.
+3.3 V
DC
nominal.
Internal Connection.
Connect this pin to GND.
20
OSCo
21
OSCi
22
23
24
25
26
IC
GND
NC
V
DD
IC
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