®
®
ADS-238Q
12-Bit, 20MHz, Low Power
Sampling A/D Converters
INNOVATION and EXCELLENCE
FEATURES
·
·
·
·
·
·
·
20MHz sampling rate
Low Power, 100mW, max
100MHz full power input bandwidth
Integral sample-and-hold
Single +3V supply operation
TTL compatible digital output
Offset binary output coding
INPUT/OUTPUT CONNECTIONS
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
FUNCTION
GND
CLK
N.C.
V
S
V
S
V
S
V
S
V
S
V
S
V
REF–
V
REF+
N.C.
N.C.
N.C.
GND
BIAS1
BIAS2
V
CM
GND
V
IN+
V
IN–
GND
PIN
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
FUNCTION
V
S
BIT 12 (LSB)
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GENERAL DESCRIPTION
The ADS-238Q is a monolithic, 12-bit, 20MHz, sampling
analog-to-digital converter fabricated in a CMOS process.
The converter is designed for applications where high speed,
wide bandwidth and low power dissipation are essential.
These characteristics are provided through the use of a fully
differential pipeline A/D architecture with digital error
correction logic for the eleven most significant bits.
The ADS-238Q offers excellent dynamic performance while
consuming only 79mW, typical. The power dissipation is
approximately proportional to the sampling rate, thus the
ADS-238Q is ideal for low power applications between 1 and
20 MHz. With low distortion and high dynamic range, this
device provides the performance required for imaging,
telecommunications, multimedia, and instrumentation
applications.
The ADS-238Q is available in a 44-pin (plastic) TQFP
package and operates over the commercial 0°C to 70°C
temperature range.
Note:
Recommend that N.C. (no connect) pins be connected to analog ground.
2-Bit
Flash A/D
BIAS1 16
BIAS2 17
Bias
Current
Adjust
X2
Stage 10
32 Bit 1 (MSB)
33 Bit 2
34 Bit 3
35 Bit 4
36 Bit 5
37 Bit 6
38 Bit 7
39 Bit 8
40 Bit 9
41 Bit 10
42 Bit 11
43 Bit 12 (LSB)
å
+
–
2-Bit
Flash A/D
2-Bit
DAC
X2
Stage 1
V
REF+
11
V
REF–
10
Reference
Input
Digital Delay
and Error
Correction
å
+
–
V
IN+
20
V
IN–
21
S/H
2-Bit
Flash A/D
2-Bit
DAC
V
CM
18
Common Mode
Voltage Reference
Clock
4 to 9, 44
+V
S
1, 15, 19, 22 to 31
GND
2 CLK
Figure 1. ADS-238Q Functional Block Diagram
DATEL, Inc., 11 Cabot Boulevard, Mansfield, MA 02048 (U.S.A.)
·
Tel: (508)339-3000 Fax: (508)339-6356
·
For immediate assistance: (800) 233-2765
®
®
ADS-238Q
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
Supply Voltage, V
S
(Pins 4-9,44)
Input Voltages:
Analog Input, V
IN+
, V
IN–
(Pin 20, 21)
V
REF–
, V
REF+,
(Pin 10, 11)
CLK,
(Pin 2)
Lead Temperature
(10 seconds)
LIMITS
–0.5 to +6
UNITS
Volts
DYNAMIC PERFORMANCE
Differential Phase
Differential Gain
Aperature Uncertainty
Aperture Delay Time,
t
AP
Data Latency
A/D Conversion Rate
DIGITAL OUTPUTS
Logic "1"
Logic "0"
CLK to Output Delay Time, t
D
POWER REQUIREMENTS
Supply Voltages, VS
Supply Current, I
S
Power Dissipation
Power Supply Rejection Ratio
PHYSICAL/ENVIRONMENTAL
Operating Temp. Range, Case
Storage Temperature Range
Package Type
Weight
0
—
+70
°C
–65
—
+125
°C
44-pin (leaded), plastic thin quad flat package
0.2 grams
2.8
—
—
—
3.3
24
79
63
3.6
30
100
—
Volts
mA
mW
dB
80% V
S
—
4
95% V
S
0.1
8
—
0.4
12
Volts
Volts
ns
—
—
—
—
—
20
0.2
0.5
10
5
7.5
—
—
—
—
—
—
—
Degrees
%
ps rms
ns
Cycles
MHz
–0.5 to (+V
S
+0.5)
–0.5 to (+V
S
+0.5)
–0.5 to (+V
S
+0.5)
+300
Volts
Volts
Volts
°C
FUNCTIONAL SPECIFICATIONS
(T
A
= T
MIN
to T
MAX
, V
S
= 3.3V, V
REF–
= 1.15V, V
REF+
= 2.15V, V
CM
= 1.65V, CLK
Frequency = 20MHz, BIAS1 = 90µA, BIAS2 = 9.5µA, Duty Cycle = 50% and
Differential Input, unless otherwise specified.)
ANALOG INPUTS
MIN.
TYP.
MAX. UNITS
Differential Input Voltage Range
Common Mode Input Voltage
Input Capacitance
Input Bandwidth, Large Signal
DIGITAL INPUTS
Logic Levels
Logic "1"
Logic "0"
Logic Loading "1"
Logic Loading "0"
Input Capacitance
REFERENCE VOLTAGES
Reference Input Voltage Range
(V
REF+
- V
REF–
)
Negative Reference Voltage
(V
REF–
)
Positive Reference Voltage
(V
REF+
)
Common Mode Output Voltage
(V
CM
)
STATIC PERFORMANCE
Resolution
Differential Nonlinearity
Integral Nonlinearity
Common Mode rejection ratio
No Missing Codes
Offset, Mid-Scale
Gain Error
DYNAMIC PERFORMANCE
Peak Harmonics
F
IN
= 5MHz
F
IN
= 10MHz
Total Harmonics Distortion
F
IN
= 5MHz
F
IN
= 10MHz
Signal-to-Noise Ratio
(w/o distortion)
F
IN
= 5MHz
F
IN
= 10MHz
Signal-to-Noise Ratio
(and distortion)
F
IN
= 5MHz
F
IN
= 10MHz
Effective Number of Bits
F
IN
= 5MHz
F
IN
= 10MHz
62
—
—
—
59
—
57
—
9.2
—
70
61
–68
–60
62
58
61
56
9.8
9.0
—
—
–61
—
—
—
—
—
—
—
dB
dB
dB
dB
dB
dB
dB
dB
Bits
Bits
—
—
—
—
12
—
—
12
±0.6
±3.0
55
—
±1.0
0.3
—
—
—
—
—
—
—
Bits
LSB
LSB
dB
Bits
%FSR
%
0.6
—
—
1.3
1.0
1.15
2.15
1.65
1.7
—
—
1.8
Volts
Volts
Volts
Volts
80% V
S
—
—
—
—
—
—
—
—
1.8
—
20% V
S
±1
±1
—
Volts
Volts
µA
µA
pF
±0.6
1.2
—
—
±1.0
1.65
1.4
120
±1.7
1.9
—
—
Volts
Volts
pF
MHz
TECHNICAL NOTES
Differential Analog Input
The analog input is a fully differential input that can be
configured in various ways depending on whether a single-
ended or differential, AC or DC coupled input is required.
An AC coupled input is most readily implemented using a
transformer (1:1 with a center tap on the secondary
winding) as illustrated in Figures 2, Typical Connection
Diagram, and 3.1, Transformer Coupled Input. To minimize
distortion, the core of the transformer must not saturate at
full scale input voltage levels. To minimize kickback noise
from the internal sample-hold a small capacitor should be
connected across the V
IN
pins (pins 20 and 21).
Figure 3.2, DC Coupled Single Ended Input, illustrates a
conversion circuit for a DC coupled single-ended input.
Power supplies and by-pass capacitors are not shown.
Reference Voltage Inputs
The ADS-238Q is designed to accept two external
reference voltages at the V
REF
input pins, see Figure 2,
Typical Connection Diagram. These reference voltages,
applied to V
REF+
(pin 11) and V
REF–
(pin 10), determine the
analog input voltage range, which is equal to ±(V
REF+
-
V
REF–
). This voltage range will be symmetric about the
common mode voltage, and for best performance should
be symmetrical about the midpoint of the supply voltage.
In order to minimize overall converter noise it is
recommended that the V
REF
pins be adequately bypassed
using a 4.7µF tantalum capacitor in parallel with a 0.01µF
ceramic capacitor. Locate the bypass capacitors as close
to the unit as possible.
2
®
®
ADS-238Q
4.7µF
Ref– In
(+1.15V)
0.01µF
+3.3V
CLK In
(3V Logic)
+
+
10µF
+3.3V
Ref+ In
(+2.15V)
0.01µF
0.1µF
1
44
V
S
+
4.7µF
0.01µF
11
12
+3.3V
Digital
Decoupling
Cap
V
Ref+
V
S
V
S
V
S
V
S
V
S
V
S
NC
CLK
GND
V
Ref–
NC
NC
90µA
9.5µA
NC
GND
Bias1
0.01µF
(+1.65V)
RF In
51
22
Bit 12 (LSB)
Bit 11
Bit 10
Bit 9
Bias2
V
CM
GND
68pF
V
IN+
V
IN–
ADS-238Q
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
34
33
Interfacing
3V Logic
Bit 1
Bit 2
GND
Minicircuit
T1-6T
23
GND
Bit 2
Bit 1(MSB)
AGND
Ferrite Bead
EXC-ELSA35
DGND
Figure 2. ADS-238QTypical Connection Diagram
R3
R3
–
+
OP191GP
(R3)/2
V
CM
R
0.01µF
R
INPUT
(
+
0.5V)
–
–
+
R2
R2
V
IN–
Minicircuit
T1-6T
R
R
R
–
+
OPA642
15pF
51W
V
IN–
OPA642
51W
V
IN+
V
CM
RF In
51
(+1.65V)
68pF
V
IN+
51W
Figure 3-1. ADS-238Q Transformer Coupled Input
Figure 3-2. ADS-238Q DC Coupled Single Ended Input
3
®
®
ADS-238Q
Common Mode Voltage Reference
The ADS-238Q has an internal common mode reference
voltage, V
CM
(pin 18). This reference voltage is typically one
half of the supply voltage and is capable of driving loads up
to 20µA. This reference is used to drive the center tap in
the transformer used in fully differential applications, or
provide level shifting in single-ended to differential
applications.
Table 1. Sample Rate Bias Current Settings
Bias Current Inputs
The bias currents shown in Table I, Sample Rate Bias
Current Settings, and Figure 4, Suggested Bias Currents
vrs Sample Rate, are designed to optimize performance of
the ADS-238Q for a given sample rate.
Figure 5, Bias Current Determination and Adjustment,
details the suggested circuits for measuring bias voltage
drops to calculate the bias currents. Adjustments to the bias
currents are made via the trim pots. The Bias1 voltage drop
is measured across TP1A and TP1B. The Bias2 voltage
drop is measured across TP2A and TP2B. Figures 6-1 and
6-2 show the relationship between the bias currents and
voltages when measured in the indicated circuit. The Bias1
and Bias2 pins should be by-passed with 0.01µF
capacitors.
SAMPLE RATE
(MHz)
1
5
10
20
BIAS1
(µA)
20
50
80
90
BIAS2
(µA)
3.5
6.5
8.0
9.5
Bias1 (µA)
90
80
70
3.4
3.2
Bias1
30
60
90
120
150
VBias1
2.19
2.53
2.79
3
3.22
Bias Current (µA)
60
50
40
30
20
10
0
0
5
10
15
20
VBias1 (V)
Bias2 (µA)
3.0
2.8
2.6
2.4
2.2
2.0
0
30
60
90
120
150
180
Sample Rate (MHz)
Figure 4. Suggested Bias Current vrs Sample Rate
IBias1 (µA)
Figure 6-1. Bias1 Voltage vrs Bias1 Current
IBias2
3
6
9
12
15
VBias2
0.6975
0.7535
0.796
0.8295
0.8595
TP1A
TP2A
100k
100k
4.75k
Bias1
500k
4.7V
+
4.7µF
0.01µF
500k
100k
Bias2
0.01µF
100k
100k
0.01µF
0.90
0.85
VBias2 (V)
TP2B
0.80
0.75
0.70
0.65
0.60
0
3
6
9
12
15
18
TP1B
IBias2 (µA)
Figure 6-2. Bias2 Voltage vrs Bias2 Current
Figure 5. Bias Current Determination and Adjustment
4
®
®
ADS-238Q
Clock
The ADS-238Q accepts a low voltage CMOS logic level at
the clock input (CLK, pin 2). The clock duty cycle must be
held to within 50% +/-3% because consecutive stages of
the A-to-D are clocked in opposite phase. A duty cycle
other than this will reduce the settling time available for
every other stage, there by degrading dynamic
performance.
For optimum performance at high input frequencies the
clock must have low jitter, and rise/fall times less than 2ns.
Over/undershoot should be avoided. Clock jitter causes
the noise floor to increase proportional to the input
frequency. To reduce crosstalk, and hence jitter, clock
traces on the PC board should be kept as short as
possible with transmission line practices employed.
Digital Outputs
The digital output data is provided in offset binary format,
at 3.3V CMOS logic levels, and is available 7.5 clock
cycles after the data is sampled. The output data is invalid
for the first 20 clock cycles when the ADS-238Q is first
powered up.
The clock to output delay is typically 8ns, but will change
as a function of the supply voltage, V
S
. Figure 7, Clock to
Output Delay vrs V
S
, shows this relationship.
A negative full scale input results in an all zeros output
code (0000 0000 0000). A positive full scale input results
in an all ones output code (1111 1111 1111).
The input is sampled during the high-to-low transition of
the input clock. Output data should be latched during the
low-to-high clock transition as shown in Figure 8, Timing
Diagram.
10.0
Clock to Output Delay (ns)
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
2.5
2.8
3.1
3.4
3.7
V
S
Figure 7. Clock to Output Delay vrs V
S
Power Supplies and Grounding
The ADS-238Q is powered from a single 3.3V supply. The
converters should be mounted on a board that provides
separate low impedance paths for the analog and digital
supplies and grounds. For best performance the 3.3V
supply should be clean, and linearly regulated. The power
supply should be bypassed to ground with a 10µF tantalum
capacitor in parallel with a 0.01µF ceramic capacitor.
Locate the bypass capacitors as close to the converter as
possible. Analog and digital grounds should be isolated
with a ferrite bead. See the Typical Connection Diagram,
Figure 2.
N-1
V
IN
N
t
AP
N+1
N+2
N+6
N+7
N+8
CLK
t
D
D
OUT
Figure 8. ADS-238Q Timing Diagram
N-2
N-1
N
5
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