Datasheet
Serial EEPROM Series Standard EEPROM
I
2
C BUS EEPROM (2-Wire)
BR24T256-W
General Description
BR24T256-W is a serial EEPROM of I
2
C BUS Interface Method
Features
Completely conforming to the world standard I
2
C
BUS.
All controls available by 2 ports of serial clock
(SCL) and serial data (SDA)
Other devices than EEPROM can be connected to
the same port, saving microcontroller port
1.6V to 5.5V Single Power Source Operation most
suitable for battery use
1.6V to 5.5V wide limit of operating voltage, possible
FAST MODE 400KHz operation
Page Write Mode useful for initial value write at
factory shipment
Self-timed Programming Cycle
Low Current Consumption
Prevention of Write Mistake
WP (Write Protect) Function added
Prevention of Write Mistake at Low Voltage
More than 1 million write cycles
More than 40 years data retention
Noise filter built in SCL / SDA terminal
Initial delivery state FFh
Packages
W(Typ) x D(Typ) x H(Max)
DIP-T8
9.30mm x 6.50mm x 7.10mm
DIP8K
9.27mm x 6.35mm x 8.63mm
SOP8
5.00mm x 6.20mm x 1.71mm
SSOP-B8
3.00mm x 6.40mm x 1.35mm
SOP- J8
4.90mm x 6.00mm x 1.65mm
TSSOP-B8
3.00mm x 6.40mm x 1.20mm
Figure 1.
BR24T256-W
Capacity
Bit Format
Type
BR24T256-W
BR24T256-WZ
BR24T256F-W
256Kbit
32K×8
BR24T256FJ-W
BR24T256FV-W
BR24T256FVT-W
(1) Not Recommended for New Designs. Recommend BR24T256-WZ.
Power Source
Voltage
Package
DIP-T8
(1)
DIP8K
SOP8
1.6V to 5.5V
SOP-J8
SSOP-B8
TSSOP-B8
〇Product
structure : Silicon monolithic integrated circuit
〇This
product has no designed protection against radioactive rays
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BR24T256-W
Absolute Maximum Ratings
(Ta=25ºC)
Parameter
Supply Voltage
Symbol
Vcc
Rating
-0.3 to +6.5
450 (SOP8)
450 (SOP-J8)
300 (SSOP-B8)
Power Dissipation
Pd
330 (TSSOP-B8)
800 (DIP-T8
(1)
)
852 (DIP8K)
Storage Temperature
Operating Temperature
Input Voltage /
Output Voltage
Junction
Temperature
Electrostatic discharge
voltage
(human body model)
Tstg
Topr
-
Tjmax
V
ESD
-65 to +150
-40 to +85
-0.3 to Vcc+1.0
150
-4000 to +4000
°C
°C
V
°C
V
mW
Unit
V
Remark
Datasheet
Derate by 4.5mW/°C when operating above Ta=25°C
Derate by 4.5mW/°C when operating above Ta=25°C
Derate by 3.0mW/°C when operating above Ta=25°C
Derate by 3.3mW/°C when operating above Ta=25°C.
Derate by 8.0mW/°C when operating above Ta=25°C
Derate by 8.52mW/°C when operating above Ta=25°C
When mounted (on 114.5 mm × 101.5 mm × 1.6 mm thick, glass
epoxy on single-layer substrate).
The Max value of input voltage / output voltage is not over 6.5V.
When the pulse width is 50ns or less, the Min value of input voltage
/ output voltage is not lower than -1.0V.
Junction temperature at the storage condition
(1) Not Recommended for New Designs. Recommend BR24T256-WZ.
Memory Cell Characteristics
(Ta=25ºC, Vcc=1.6V to 5.5V)
Parameter
Write Cycles
(1)
Data Retention
(1)
(1) Not 100% TESTED
Limit
Min
Typ
1,000,000
-
40
-
Max
-
-
Unit
Times
Years
Recommended Operating Ratings
Parameter
Power Source Voltage
Input Voltage
Symbol
Vcc
V
IN
Rating
1.6 to 5.5
0 to Vcc
Unit
V
DC Characteristics
(Unless otherwise specified, Ta=-40ºC to +85ºC, Vcc=1.6V to 5.5V)
Parameter
Input High Voltage1
Input Low Voltage1
Input High Voltage2
Input Low Voltage2
Output Low Voltage1
Output Low Voltage2
Input Leakage Current
Output Leakage Current
Supply Current (Write)
Supply Current (Read)
Standby Current
Symbol
V
IH1
V
IL1
V
IH2
V
IL2
V
OL1
V
OL2
I
LI
I
LO
I
CC1
I
CC2
I
SB
Limit
Min
0.7Vcc
-0.3
-0.3
-
-
-1
-1
-
-
-
(2)
Typ
-
-
-
-
-
-
-
-
-
-
-
Max
Vcc+1.0
+0.3Vcc
Vcc+1.0
+0.2Vcc
0.4
0.2
+1
+1
2.5
0.5
2.0
Unit
V
V
V
V
V
V
µA
µA
mA
mA
µA
1.7V≤Vcc≤5.5V
1.7V≤Vcc≤5.5V
1.6V≤Vcc<1.7V
1.6V≤Vcc<1.7V
Conditions
0.8Vcc
(2)
I
OL
=3.0mA, 2.5V≤Vcc≤5.5V (SDA)
I
OL
=0.7mA, 1.6V≤Vcc<2.5V (SDA)
V
IN
=0 to Vcc
V
OUT
=0 to Vcc (SDA)
Vcc=5.5V, f
SCL
=400kHz, t
WR
=5ms,
Byte write, Page write
Vcc=5.5V, f
SCL
=400kHz
Random read, current read, sequential read
Vcc=5.5V, SDA,SCL=Vcc
A0,A1,A2=GND,WP=GND
(2) When the pulse width is 50ns or less, it is -1.0V.
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BR24T256-W
AC Characteristics
(Unless otherwise specified, Ta=-40ºC to +85ºC, Vcc=1.6V to 5.5V)
Parameter
Clock Frequency
Data Clock High Period
Data Clock Low Period
SDA,SCL(INPUT) Rise Time
(1)
SDA,SCL (INPUT)Fall Time
(1)
SDA(OUTPUT)Fall Time
(1)
Start Condition Hold Time
Start Condition Setup Time
Input Data Hold Time
Input Data Setup Time
Output Data Delay Time
Output Data Hold Time
Stop Condition Setup Time
Bus Free Time
Write Cycle Time
Noise Spike Width (SDA and SCL)
WP Hold Time
WP Setup Time
WP High Period
(1) Not 100% TESTED.
Condition Input Data Level:V
IL
=0.2×Vcc V
IH
=0.8×Vcc
Input Data Timing Reference Level: 0.3×Vcc/0.7×Vcc
Output Data Timing Reference Level: 0.3×Vcc/0.7×Vcc
Rise/Fall Time : ≤20ns
Datasheet
Symbol
f
SCL
t
HIGH
t
LOW
t
R
t
F1
t
F2
t
HD:STA
t
SU:STA
t
HD:DAT
t
SU:DAT
t
PD
t
DH
t
SU:STO
t
BUF
t
WR
t
I
t
HD:WP
t
SU:WP
t
HIGH:WP
Limit
Min
-
0.6
1.2
-
-
-
0.6
0.6
0
100
0.1
0.1
0.6
1.2
-
-
1.0
0.1
1.0
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
400
-
-
1.0
1.0
0.3
-
-
-
-
0.9
-
-
-
5
0.1
-
-
-
Unit
kHz
µs
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
µs
µs
ms
µs
µs
µs
µs
Serial Input / Output Timing
tR
SCL
70%
30%
70% 70%
30%
tF1
tHIGH
70%
30%
70%
30%
70%
DATA(1)
DATA(n)
ACK
ACK
70%
tHD:STA
70%
70%
30%
70%
tLOW
tSU:DAT
tHD:DAT
70%
30%
D1
D0
tWR
30%
70%
SDA
(入力)
(INPUT)
SDA
(出力)
(OUTPUT)
SDA
(output)
tBUF
tPD
70%
30%
70%
tDH
30%
30%
70%
30%
30%
tSU:WP
tSU:WP
○
Input read at the rise edge of SCL
○
Data output in sync with the fall of SCL
30%
tF2
tHD:WP
STOP CONDITION
STOP CONDITION
Figure 2-(d). WP Timing at Write Execution
Figure 2-(a). Serial Input / Output Timing
70%
70%
70%
DATA(1)
DATA(1)
D1
D1
D0
D0
ACK
ACK
DATA(n)
DATA(n)
ACK
ACK
tHIGH:WP
tHIGH:WP
70%
70%
tSU:STA
70%
30%
tHD:STA
tSU:STO
tWR
tWR
30%
70%
70%
70%
Fig1-(4) Write
70%
cycle timing
START CONDITION
30%
30%
STOP CONDITION
Fig1-(5) WP timing at write execution
Fig1-(6) WP timing at write cancel
Figure 2-(e). WP Timing at Write Cancel
Figure 2-(b). Start-Stop Bit Timing
STOP CONDITION
START CONDITION
D0
ACK
70%
70%
write data
(n-th address)
tWR
STOP CONDITION
START CONDITION
Figure 2-(c). Write Cycle Timing
Fig1-(5) WP timing at write execution
Fig1-(6) WP timing at write cancel
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BR24T256-W
Block Diagram
A0
1
256Kbit EEPROM Array
8bit
Datasheet
8
VCC
A1
2
Address
Decoder
15bit
Word
Address Register
Data
Register
7
WP
START
STOP
A2 3
Control Circuit
ACK
6
SCL
GND 4
High Voltage
Generating Circuit
Power Source
Voltage Detection
5 SDA
Figure 3. Block Diagram
Pin Configuration
(TOP VIEW)
A0
1
2
BR24T256-W
A2
3
6
5
SCL
SDA
8
VCC
A1
7
WP
GND
4
Pin Descriptions
Terminal
Name
A0
A1
A2
GND
SDA
SCL
WP
VCC
Input/
Output
Input
Input
Input
-
Input/
Output
Input
Input
-
Descriptions
Slave address setting*
Slave address setting*
Slave address setting*
Reference voltage of all input / output, 0V
Serial data input serial data output
Serial clock input
Write protect terminal
Connect the power source.
*A0, A1 and A2 are not allowed to use as open.
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BR24T256-W
Typical Performance Curves
(The following values are Typ)
Datasheet
1.2
0.2
SPEC
SPEC
0.1
Input Low Voltage:V
IL1
( V)
Input High Voltage:V
IH1
( V)
1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0.8
Ta=-40℃
Ta= 25℃
Ta= 85℃
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.6
0.4
0.2
0
0
1
2
3
4
5
6
Supply Voltage: Vcc(V)
-0.6
0
1
2
3
4
5
6
Supply Voltage: Vcc(V)
Figure 5. Input Low Voltage1,2 vs Supply Voltage
(A0, A1, A2, SCL, SDA, WP)
Figure 4. Input High Voltage1,2 vs Supply Voltage
(A0, A1, A2, SCL, SDA, WP)
1
Ta=-40℃
Ta= 25℃
Ta= 85℃
1
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.6
SPEC
Output Low Voltage2: VOL2(V)
Output Low Voltage1: VOL1(V)
0.8
0.8
0.6
0.4
0.4
SPEC
0.2
0.2
0
0
1
2
3
4
5
6
Output Low Current: IOL(mA)
0
0
1
2
3
4
5
6
Output Low Current: IOL(mA)
Figure 6. Output Low Voltage1 vs Output Low Current
(Vcc=2.5V)
Figure 7. Output Low Voltage2 vs Output Low Current
(Vcc=1.6V)
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TSZ02201-0R2R0G100140-1-2
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