ZL49010/11, ZL49020/21, ZL49030/31
Wide Dynamic Range DTMF Receiver
Data Sheet
Features
•
•
•
•
•
•
•
•
•
Wide dynamic range (50 dB) DTMF Receiver
Call progress (CP) detection via cadence
indication
4-bit synchronous serial data output
Software controlled guard time for ZL490x0
Internal guard time circuitry for ZL490x1
Powerdown option (ZL4901x & ZL4903x)
3.579 MHz crystal or ceramic resonator (ZL4903x
and ZL4902x)
External clock input (ZL4901x)
Guarantees non-detection of spurious tones
Ordering Information
ZL49010/11DAA
ZL49020/21DAA
ZL49030/31DCA
ZL49030/31DCB
ZL49030/31DDA
ZL49030/31DDB
ZL49010/11DAA1
ZL49020/21DAA1
ZL49030/31DCE1
ZL49030/31DCF1
Tubes
Tubes
Tubes
Tape & Reel
Tubes
Tape & Reel
Tubes
Tubes
Tubes, Bake & Drypack
Tape & Reel,
Bake & Drypack
ZL49030/31DDE1 20 Pin SSOP* Tubes, Bake & Drypack
ZL49030/31DDF1 20 Pin SSOP* Tubes, Bake & Drypack
*Pb Free Matte Tin
-40°C to +85°C
8 Pin PDIP
8 Pin PDIP
18 Pin SOIC
18 Pin SOIC
20 Pin SSOP
20 Pin SSOP
8 Pin PDIP*
8 Pin PDIP*
18 Pin SOIC*
18 Pin SOIC*
February 2007
Applications
•
•
•
Integrated telephone answering machine
End-to-end signalling
Fax Machines
Description
The ZL490xx is a family of high performance DTMF
receivers which decode all 16 tone pairs into a 4-bit
binary code. These devices incorporate an AGC for
wide dynamic range and are suitable for end-to-end
signalling. The ZL490x0 provides an early steering
(ESt) logic output to indicate the detection of a DTMF
signal and requires external software guard time to
validate the DTMF digit. The ZL490x1, with preset
internal guard times, uses a delay steering (DStD)
logic output to indicate the detection of a valid DTMF
digit. The 4-bit DTMF binary digit can be clocked out
synchronously at the serial data (SD) output. The SD
pin is multiplexed with call progress detector output. In
the presence of supervisory tones, the call progress
detector circuit indicates the cadence (i.e., envelope)
of the tone burst. The cadence information can then be
processed by an external microcontroller to identify
PWDN
VDD
VSS
1
Voltage
Bias Circuit
Steering
Circuit
High
Group
Filter
Anti-
alias
Filter
Dial
Tone
Filter
Low
Group
Filter
Digital
Detector
Algorithm
Code
Converter
and
Latch
Digital
Guard
Time
3
Parallel to
Serial
Converter
& Latch
ESt
or
DStD
ACK
AGC
Mux
SD
OSC2
OSC1
(CLK)
2
Oscillator
and
Clock
Circuit
To All Chip Clocks
Energy
Detection
1.
ZL49010/1 and ZL49030/1 only.
2.
ZL49020/1 and ZL49030/1 only.
3.
ZL490x1 only.
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2007, Zarlink Semiconductor Inc. All Rights Reserved.
ZL49010/11, ZL49020/21, ZL49030/31
Data Sheet
specific call progress signals. The ZL4902x and ZL4903x can be used with a crystal or a ceramic resonator without
additional components. A power-down option is provided for the ZL4901x and ZL4903x.
ZL49030DD/1DD
NC
NC
INPUT
PWDN
NC
OSC2
OSC1
VSS
NC
NC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC
NC
VDD
NC
ESt/DStD
NC
ACK
SD
NC
NC
ZL49010/1
INPUT
PWDN
CLK
VSS
1
2
3
4
8
7
6
5
VDD INPUT
ESt/
DStD OSC2
ACK
SD
OSC1
VSS
ZL49020/1
1
2
3
4
8
7
6
5
VDD
ESt/
DStD
ACK
SD
NC
INPUT
PWDN
OSC2
NC
OSC1
NC
NC
VSS
ZL49030DC/1DC
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
VDD
NC
NC
ESt/DStD
NC
ACK
NC
SD
NC
8 PIN PLASTIC DIP
18 PIN PLASTIC SOIC
20 PIN SSOP
Figure 2 - Pin Connections
Pin Description
Pin #
4903xDD
3
6
7
4903xDC
2
4
6
4902x
1
2
3
4901x
1
-
3
Name
INPUT
OSC2
OSC1
(CLK)
Description
DTMF/CP Input.
Input signal must be AC coupled via
capacitor.
Oscillator Output.
Oscillator/Clock Input.
This pin can either be driven by:
1) an external digital clock with defined input logic
levels. OSC2 should be left open.
2) connecting a crystal or ceramic resonator between
OSC1 and OSC2 pins.
Ground.
(0 V)
Serial Data/Call Progress Output.
This pin serves the
dual function of being the serial data output when clock
pulses are applied after validation of DTMF signal, and
also indicates the cadence of call progress input. As
DTMF signal lies in the same frequency band as call
progress signal, this pin may toggle for DTMF input. The
SD pin is at logic low in powerdown state.
Acknowledge Pulse Input.
After ESt or DStD is high,
applying a sequence of four pulses on this pin will then
shift out four bits on the SD pin, representing the decoded
DTMF digit. The rising edge of the first clock is used to
latch the 4-bit data prior to shifting. This pin is pulled
down internally. The idle state of the ACK signal should
be low.
8
13
9
11
4
5
4
5
V
SS
SD
14
13
6
6
ACK
2
Zarlink Semiconductor Inc.
ZL49010/11, ZL49020/21, ZL49030/31
Pin Description (continued)
Pin #
4903xDD
16
4903xDC
15
4902x
7
4901x
7
Name
ESt
(ZL490x0)
Data Sheet
Description
Early Steering Output.
A logic high on ESt indicates that
a DTMF signal is present. ESt is at logic low in
powerdown state.
Delayed Steering Output.
A logic high on DStD
indicates that a valid DTMF digit has been detected. DStD
is at logic low in powerdown state.
Positive Power Supply (5 V Typ.)
Performance of the
device can be optimized by minimizing noise on the
supply rails. Decoupling capacitors across V
DD
and V
SS
are therefore recommended.
No Connection.
Pin is unconnected internally.
DStD
(ZL490x1)
18
18
8
8
V
DD
1,2,5,9,
10,11,12,
15,17,19,20
4
1,5,7,8,
10, 12,
14,16,
17
3
-
-
NC
-
2
PWDN
Power Down Input.
A logic high on this pin will power
down the device to reduce power consumption. This pin
is pulled down internally and can be left open if not used.
ACK pin should be at logic ’0’ to power down device.
Device
Type
ZL49010
ZL49011
ZL49020
ZL49021
ZL49030
ZL49031
8 Pin
x
x
x
x
18 Pin
20 Pin
PWDN
x
x
2 Pin
OSC
Ext
CLK
x
x
ESt
x
DStD
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Table 1 - Summary of ZL490x0/1 Product Family
Change Summary
The following table summarizes the changes from the July 2006 issue.
Page
2
2
Item
Figure 2
Pin Description
Description
Added ordering codes to Pin Connection diagram.
Added 20 pin description to the table.
3
Zarlink Semiconductor Inc.
ZL49010/11, ZL49020/21, ZL49030/31
Functional Description
Data Sheet
The ZL490xxs are high performance and low power consumption DTMF receivers. These devices provide wide
dynamic range DTMF detection and a serial decoded data output. These devices also incorporate an energy
detection circuit. An input voiceband signal is applied to the devices via a series decoupling capacitor. Following the
unity gain buffering, the signal enters the AGC circuit followed by an anti-aliasing filter. The bandlimited output is
routed to a dial tone filter stage and to the input of the energy detection circuit. A bandsplit filter is then used to
separate the input DTMF signal into high and low group tones. The high group and low group tones are then
verified and decoded by the internal frequency counting and DTMF detection circuitry. Following the detection
stage, the valid DTMF digit is translated to a 4-bit binary code (via an internal look-up ROM). Data bits can then be
shifted out serially by applying external clock pulses.
Automatic Gain Control (AGC) Circuit
As the device operates on a single power supply, the input signal is biased internally at approximately VDD/2. With
large input signal amplitude (between 0 and approximately -30 dBm for each tone of the composite signal), the
AGC is activated to prevent the input signal from being clipped. At low input level, the AGC remains inactive and the
input signal is passed directly to the hardware DTMF detection algorithm and to the energy detection circuit.
Filter and Decoder Section
The signal entering the DTMF detection circuitry is filtered by a notch filter at 350 and 440 Hz for dial tone rejection.
The composite dual-tone signal is further split into its individual high and low frequency components by two 6
th
order switched capacitor bandpass filters. The high group and low group tones are then smoothed by separate
output filters and squared by high gain limiting comparators. The resulting squarewave signals are applied to a
digital detection circuit where an averaging algorithm is employed to determine the valid DTMF signal. For
ZL490x0, upon recognition of a valid frequency from each tone group, the early steering (ESt) output will go high,
indicating that a DTMF tone has been detected. Any subsequent loss of DTMF signal condition will cause the ESt
pin to go low. For ZL490x1, an internal delayed steering counter validates the early steering signal after a
predetermined guard time which requires no external components. The delayed steering (DStD) will go high only
when the validation period has elapsed. Once the DStD output is high, the subsequent loss of early steering signal
due to DTMF signal dropout will activate the internal counter for a validation of tone absent guard time. The DStD
output will go low only after this validation period.
Energy Detection
The output signal from the AGC circuit is also applied to the energy detection circuit. The detection circuit consists
of a threshold comparator and an active integrator. When the signal level is above the threshold of the internal
comparator (-35 dBm), the energy detector produces an energy present indication on the SD output. The integrator
ensure the SD output will remain at high even though the input signal is changing. When the input signal is
removed, the SD output will go low following the integrator decay time. Short decay time enables the signal
envelope (or cadence) to be generated at the SD output. An external microcontroller can monitor this output for
specific call progress signals. Since presence of speech and DTMF signals (above the threshold limit) can cause
the SD output to toggle, both ESt (DStD) and SD outputs should be monitored to ensure correct signal identification.
As the energy detector is multiplexed with the digital serial data output at the SD pin, the detector output is selected
at all times except during the time between the rising edge of the first pulse and the falling edge of the fourth pulse
applied at the ACK pin.
Serial Data (SD) Output
When a valid DTMF signal burst is present, ESt or DStD will go high. The application of four clock pulses on the
ACK pin will provide a 4-bit serial binary code representing the decoded DTMF digit on the SD pin output. The rising
edge of the first pulse applied on the ACK pin latches and shifts the least significant bit of the decoded digit on the
SD pin. The next three pulses on ACK pin will shift the remaining latched bits in a serial format (see Figure 5). If less
than four pulses are applied to the ACK pin, new data cannot be latched even though ESt/DStD can be valid. Clock
pulses should be applied to clock out any remaining data bits to resume normal operation. Any transitions in excess
4
Zarlink Semiconductor Inc.
ZL49010/11, ZL49020/21, ZL49030/31
Data Sheet
of four pulses will be ignored until the next rising edge of the ESt/DStD. ACK should idle at logic low. The 4-bit
binary representing all 16 standard DTMF digits are shown in Table 2.
Powerdown Mode (ZL4901x/4903x)
The ZL4901x/4903x devices offer a powerdown function to preserve power consumption when the device is not in
use. A logic high can be applied at the PWDN pin to place the device in powerdown mode. The ACK pin should be
kept at logic low to avoid undefined ESt/DStD and SD outputs (see Table 3).
F
LOW
697
697
697
770
770
770
852
852
852
941
941
941
697
770
852
941
F
HIGH
1209
1336
1477
1209
1336
1477
1209
1336
1477
1336
1209
1477
1633
1633
1633
1633
DIGIT
1
2
3
4
5
6
7
8
9
0
*
#
A
B
C
D
b
3
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
b
2
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
b
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
b
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0= LOGIC LOW, 1= LOGIC HIGH
Note: b0=LSB of decoded DTMF digit and shifted out first.
Table 2 - Serial Decode Bit Table
ACK (input)
low
low
high
high
PWDN (input)
low
high
+
low
high
ESt/DStD (output)
Refer to Fig. 4 for
timing waveforms
low
low
undefined
Table 3 - Powerdown Mode
SD (output)
Refer to Fig. 4 for
timing waveforms
low
undefined
undefined
ZL4901x/4903x
status
normal operation
powerdown mode
undefined
undefined
Note:
+
=enters powerdown mode on the rising edge.
5
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