ZL50057GAC datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Wireless rf/communication> Telecom circuit> ZL50057GAC

ZL50057GAC: DescriptionTELECOM, DIGITAL TIME SWITCH, PBGA256; CategoryWireless rf/communication Telecom circuit; File Size737KB，108 Pages; ManufacturerZarlink Semiconductor (Microsemi); Websitehttp://www.zarlink.com/

Download Datasheet Parametric Compare View All

ZL50057GAC Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	ZL50057GAC	-	-	View	Buy Now

ZL50057GAC Overview

TELECOM, DIGITAL TIME SWITCH, PBGA256

ZL50057GAC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Zarlink Semiconductor (Microsemi)
package instruction	BGA, BGA272,20X20,50
Reach Compliance Code	compli
JESD-30 code	S-PBGA-B272
JESD-609 code	e0
length	27 mm
Humidity sensitivity level	1
Number of functions	1
Number of terminals	272
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA272,20X20,50
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	225
power supply	1.8,3.3 V
Certification status	Not Qualified
Maximum seat height	2.54 mm
Nominal supply voltage	1.8 V
surface mount	YES
Telecom integrated circuit types	DIGITAL TIME SWITCH
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	27 mm

Preview

Download Datasheet

View All

ZL50057/8

12 K-Channel Digital Switch with High Jitter

Tolerance, Per Stream Rate Conversion (2, 4, 8,

16, or 32 Mbps), and 48 Inputs and 48 Outputs

Data Sheet

Features

•

12,288-channel x 12,288-channel non-blocking

unidirectional switching.The Backplane and Local

inputs and outputs can be combined to form a

non-blocking switching matrix with 48 input

streams and 48 output streams

8,192-channel x 4,096-channel non-blocking

Backplane input to Local output stream switch

4,096-channel x 8,192-channel non-blocking

Local input to Backplane output stream switch

8,192-channel x 8,192-channel non-blocking

Backplane input to Backplane output switch

4,096-channel x 4,096-channel non-blocking

Local input to Local output stream switch

Rate conversion on all data paths, Backplane-to-

Local, Local-to-Backplane, Backplane-to-

Backplane and Local-to-Local streams

Backplane port accepts 32 input and 32 output

ST-BUS streams with data rates of 2.048 Mbps,

4.096 Mbps, 8.192 Mbps or 16.384 Mbps in any

combination, or a fixed allocation of 16 input and

16 output streams at 32.768 Mbps

Local port accepts 16 input and 16 output ST-

BUS streams with data rates of 2.048 Mbps,

DD_IO

DD_CORE

January 2006

Ordering Information

ZL50057GAC

272-Ball PBGA

ZL50058GAC

256 Ball PBGA

ZL50058GAG2 256 Ball PBGA**

**Pb Free Tin/Silver/Copper

-40°C to +85°C

4.096 Mbps, 8.192 Mbps or 16.384 Mbps in any

combination, or a fixed allocation of 8 input and 8

output streams at 32.768 Mbps

•

Exceptional input clock jitter tolerance (17 ns for

16 Mbps or lower data rates, 14 ns for 32 Mbps)

Per-stream channel and bit delay for Local and

Backplane input streams

Per-stream advancement for Local and

Backplane output streams

Constant 2-frame throughput delay for frame

integrity

Per-channel high impedance output control for

Local and Backplane streams

Per-channel driven-high output control for Local

and Backplane streams

RESET

ODE

Trays

•

SS (GND)

BSTi0-31

Backplane Data Memories

(8,192 channels)

Local

Interface

LSTi0-15

BSTo0-31

BCST0-3

BORS

Backplane

Interface

Backplane

Connection Memory

(8,192 locations)

Local

Connection Memory

(4,096 locations)

Local

Interface

LSTo0-15

LCST0-1

Local Data Memories

(4,096 channels)

Input

Timing Unit

Output

Timing

Unit

LORS

FP8i

FP8o

FP16o

C8o

C16o

C8i

PLL

Microprocessor Interface

and Internal Registers

Test Port

DD_PLL

DS CS R/W

A14-0

DTA

D15-0

TMS TDi TDo TCK TRST

Figure 1 - ZL50057/8 Functional Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

ZL50057/8

Device Overview

Data Sheet

The ZL50057 and ZL50058 are two different packages of the same device. The ZL50057/8 has two data ports, the

Backplane and the Local port. The Backplane port has two independent modes of operation, either 32 input and 32

output streams operated at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps, in any combination, or 16 input

and 16 output streams operated at 32.768 Mbps. The Local port has two independent modes of operation, either 16

input and 16 output streams operated at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps, in any

combination, or 8 input and 8 output streams operated at 32.768 Mbps.

The ZL50057/8 contains two data memory blocks (Backplane and Local) to provide the following switching path

configurations:

•

Input-to-Output Unidirectional, supporting 12 K x 12 K switching

Backplane-to-Local Bi-directional, supporting 8 K x 4 K data switching,

Local-to-Backplane Bi-directional, supporting 4 K x 8 K data switching,

Backplane-to-Backplane Bi-directional, supporting 8 K x 8 K data switching.

Local-to-Local Bi-directional, supporting 4 K x 4 K data switching.

The device contains two connection memory blocks, one for the Backplane output and one for the Local output.

Data to be output on the serial streams may come from either of the data memories (Connection Mode) or directly

from the connection memory contents (Message Mode).

In Connection Mode, the contents of the connection memory define, for each output stream and channel, the

source stream and channel (stored in data memory) to be switched.

In Message Mode, microprocessor data can be written to the connection memory for broadcast on the output

streams on a per channel basis. This feature is useful for transferring control and status information to external

circuits or other ST-BUS devices.

The device uses a master frame pulse (FP8i) and master clock (C8i) to define the input frame boundary and timing

for both the Backplane port and the Local port. The device will automatically detect whether an ST-BUS or a GCI-

Bus style frame pulse is being used. There is a two-frame delay from the time RESET is de-asserted to the

establishment of full switch functionality. During this period, the input frame pulse format is determined before

switching begins.

The device provides FP8o, FP16o, C8o and C16o outputs to support external devices connected to the outputs of

the Backplane and Local ports.

A non-multiplexed Motorola microprocessor port allows programming of the various device operation modes and

switching configurations. The microprocessor port provides access for Register read/write, Connection Memory

read/write and Data Memory read-only operations. The port has a 15-bit address bus, 16-bit data bus and 4 control

signals. The microprocessor may monitor channel data in the Backplane and Local data memories.

The mandatory requirements of the IEEE-1149.1 (JTAG) standard are fully supported via a dedicated test port.

The ZL50057 and ZL50058 are each available in one package:

•

ZL50057: a 27 mm x 27 mm body, 1.27mm ball-pitch, 272-PBGA.

ZL50058: a 17 mm x 17 mm body, 1mm ball-pitch, 256-PBGA.

Zarlink Semiconductor Inc.

ZL50057/8

Table of Contents

Data Sheet

1.0 Unidirectional and bi-directional Switching Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

1.1 Flexible Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

1.1.1 Non-Blocking Unidirectional Configuration (Typical System Configuration) . . . . . . . . . . . . . . . . . . 22

1.1.2 Non-Blocking bi-directional Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

1.1.3 Blocking bi-directional Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.1 Switching Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.1.1 Unidirectional Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.1.2 Backplane-to-Local Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.1.3 Local-to-Backplane Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.1.4 Backplane-to-Backplane Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.1.5 Local-to-Local Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.1.6 Port Data Rate Modes and Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.1.7 Local Port Rate Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.1.7.1 Local Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.1.7.2 Local Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.1.8 Backplane Port Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.1.8.1 Backplane Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.1.8.2 Backplane Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.2 Frame Pulse Input and Master Input Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.3 Input Frame Pulse and Generated Frame Pulse Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.4 Jitter Tolerance Improvement Circuit - Frame Boundary Discriminator. . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.5 Input Clock Jitter Tolerance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.6 Backward Compatibility with MT90870 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.0 Input and Output Offset Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.1 Input Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.1.1 Input Channel Delay Programming (Backplane and Local Input Streams) . . . . . . . . . . . . . . . . . . . 30

3.1.2 Input Bit Delay Programming (Backplane and Local Input Streams) . . . . . . . . . . . . . . . . . . . . . . . . 30

3.2 Output Advancement Programming (Backplane and Local Output Streams) . . . . . . . . . . . . . . . . . . . . . . 32

4.0 Port High Impedance Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.1 LORS Asserted LOW, Non-32Mbps Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.2 LORS Asserted LOW, 32Mbps Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.3 LORS Asserted HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.4 BORS Asserted LOW, Non-32Mbps Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.5 BORS Asserted LOW, 32Mbps Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.6 BORS Asserted HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

5.0 Data Delay Through the Switching Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.0 Bit Error Rate Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

7.0 Microprocessor Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

8.0 Device Power-up, Initialization and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

8.1 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

8.2 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

8.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

9.0 Connection Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

9.1 Local Connection Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

9.2 Backplane Connection Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

9.3 Connection Memory Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

9.3.1 Memory Block Programming Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10.0 Memory Built-In-Self-Test (BIST) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

11.0 JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

11.1 Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Zarlink Semiconductor Inc.

ZL50057/8

Table of Contents

Data Sheet

11.2 TAP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

11.2.1 Test Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

11.2.2 Test Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

11.2.2.3 The Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

11.3 Boundary Scan Description Language (BSDL) File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

12.0 Memory Address Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

12.1 Local Data Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

12.2 Backplane Data Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

12.3 Local Connection Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

12.4 Backplane Connection Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

13.0 Internal Register Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

14.0 Detailed Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

14.1 Control Register (CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

14.2 Block Programming Register (BPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

14.3 Bit Error Rate Test Control Register (BERCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

14.4 Local Input Channel Delay Registers (LCDR0 to LCDR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

14.4.1 Local Channel Delay Bits 8-0 (LCD8 - LCD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

14.5 Local Input Bit Delay Registers (LIDR0 to LIDR15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

14.5.1 Local Input Delay Bits 4-0 (LID[4:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

14.6 Backplane Input Channel Delay Registers (BCDR0 to BCDR31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

14.6.1 Backplane Channel Delay Bits 8-0 (BCD8 - BCD0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

14.7 Backplane Input Bit Delay Registers (BIDR0 to BIDR31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

14.7.1 Backplane Input Delay Bits 4-0 (BID[4:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

14.8 Local Output Advancement Registers (LOAR0 to LOAR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

14.8.1 Local Output Advancement Bits 1-0 (LOA1-LOA0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

14.9 Backplane Output Advancement Registers (BOAR0 - BOAR31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

14.9.1 Backplane Output Advancement Bits 1-0 (BOA1-BOA0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

14.10 Local Bit Error Rate (BER) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

14.10.1 Local BER Start Send Register (LBSSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

14.10.2 Local Transmit BER Length Register (LTXBLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

14.10.3 Local Receive BER Length Register (LRXBLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

14.10.4 Local BER Start Receive Register (LBSRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

14.10.5 Local BER Count Register (LBCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

14.11 Backplane Bit Error Rate (BER) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

14.11.1 Backplane BER Start Send Register (BBSSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

14.11.2 Backplane Transmit BER Length Register (BTXBLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

14.11.3 Backplane Receive BER Length Register (BRXBLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

14.11.4 Backplane BER Start Receive Register (BBSRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

14.11.5 Backplane BER Count Register (BBCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

14.12 Local Bit Rate Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

14.12.1 Local Input Bit Rate Registers (LIBRR0 - LIBRR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

14.12.2 Local Output Bit Rate Registers (LOBRR0 - LOBRR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

14.13 Backplane Bit Rate Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

14.13.1 Backplane Input Bit Rate Registers (BIBRR0 - BIBRR31). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

14.13.2 Backplane Output Bit Rate Registers (BOBRR0 - BOBRR31) . . . . . . . . . . . . . . . . . . . . . . . . . . 87

14.14 Memory BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

14.15 Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

15.0 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

16.0 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Zarlink Semiconductor Inc.

ZL50057GAC Related Products

	ZL50057GAC	ZL50057	ZL50058	ZL50058GAC	ZL50058GAG2
Description	TELECOM, DIGITAL TIME SWITCH, PBGA256	TELECOM, DIGITAL TIME SWITCH, PBGA256	TELECOM, DIGITAL TIME SWITCH, PBGA256	TELECOM, DIGITAL TIME SWITCH, PBGA256	TELECOM, DIGITAL TIME SWITCH, PBGA256
Number of functions	1	1	1	1	1
Number of terminals	272	256	256	256	256
Maximum operating temperature	85 °C	85 Cel	85 Cel	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 Cel	-40 Cel	-40 °C	-40 °C
surface mount	YES	Yes	Yes	YES	YES
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	BALL	BALL	BALL	BALL	BALL
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maker	Zarlink Semiconductor (Microsemi)	-	-	Zarlink Semiconductor (Microsemi)	Zarlink Semiconductor (Microsemi)
package instruction	BGA, BGA272,20X20,50	-	-	BGA, BGA256,16X16,40	BGA,
Reach Compliance Code	compli	-	-	compli	unknow
JESD-30 code	S-PBGA-B272	-	-	S-PBGA-B256	S-PBGA-B256
JESD-609 code	e0	-	-	e0	e1
length	27 mm	-	-	17 mm	17 mm
Package body material	PLASTIC/EPOXY	-	-	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	-	-	BGA	BGA
Package shape	SQUARE	-	-	SQUARE	SQUARE
Package form	GRID ARRAY	-	-	GRID ARRAY	GRID ARRAY
Certification status	Not Qualified	-	-	Not Qualified	Not Qualified
Maximum seat height	2.54 mm	-	-	1.8 mm	1.8 mm
Nominal supply voltage	1.8 V	-	-	1.8 V	1.8 V
Telecom integrated circuit types	DIGITAL TIME SWITCH	-	-	DIGITAL TIME SWITCH	DIGITAL TIME SWITCH
Terminal surface	Tin/Lead (Sn/Pb)	-	-	Tin/Lead (Sn/Pb)	TIN SILVER COPPER
Terminal pitch	1.27 mm	-	-	1 mm	1 mm
width	27 mm	-	-	17 mm	17 mm

Recommended Resources

KA2305 (toy) radio remote control receiving control and regulating circuit

Modulated infrared transmitter circuit

Car mileage meter circuit

Xinghua FB-40 wall fan circuit diagram

Detection status circuit

Toy car remote control circuit

I have asked many questions about WIN CE 5.0 in many groups and forums, but no one has answered! Thank you everyone!: [img]D:\1.jpg[/img] [img]D:\2.jpg[/img] I have followed the above instructions but it still doesn't work! Please give me some advice! Thank you!...; hhhhwangba Embedded System

How to deal with foreign company interviews: [table=98%][tr][td][table=98%][tr][td]Foreign companies have formed a complete and strict system for recruiting employees, and interviews also have mature procedures. However, domestic employers do no...; songbo Talking about work

Novice Fighting ARM (LPC2131), Practical Part (1): Some time ago, I saw Samsung's 4510. Finally, I have some understanding of ARM... I feel that it is impossible to learn such pure technical things in a short time. So, I only seek to know half of it.....; fishingok MCU

[Allwinner heterogeneous multi-core AI intelligent vision V853 development board evaluation] ERROR: dl file rootfs.fex size too l...: According to the official tutorial https://v853.docs.aw-ol.com/npu/npu_demo/ , test NPU Demo. After make, it prompts ERROR: dl file rootfs.fex size too largeBy consulting the information, I found that...; dql2016 Domestic Chip Exchange

Could you please tell me, experts, is the photoresist in the DMD digital micromirror positive or negative?: [size=14px]Is the photoresist in the DMD digital micromirror positive or negative? [/size]...; xujianjian TI Technology Forum

How to write large files to USB sectors: How to write a large file to a USB sector? How to write a file larger than 256M? writefile? deviceiocontrol? memory mapping? How to use these? I used WRITEFILE(), but the data written in was not corre...; chenyugang222 Embedded System

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components