LAN9217-MT datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> LAN9217-MT

LAN9217-MT: Description1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100; CategoryThe embedded processor and controller Microcontrollers and processors; File Size873KB，134 Pages; ManufacturerSMSC; Websitehttp://www.smsc.com/

Download Datasheet Parametric Compare View All

LAN9217-MT Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	LAN9217-MT	-	-	View	Buy Now

LAN9217-MT Overview

1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100

LAN9217-MT Parametric

Parameter Name	Attribute value
Maker	SMSC
Parts packaging code	QFP
package instruction	LFQFP,
Contacts	100
Reach Compliance Code	unknow
Address bus width	7
boundary scan	NO
maximum clock frequency	25 MHz
Data encoding/decoding methods	NRZI; BIPH-LEVEL(MANCHESTER)
Maximum data transfer rate	12.5 MBps
External data bus width	16
JESD-30 code	S-PQFP-G100
JESD-609 code	e3
length	14 mm
low power mode	YES
Number of serial I/Os	1
Number of terminals	100
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
width	14 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, LAN

Preview

Download Datasheet

View All

LAN9217

16-bit High-Performance

Single-Chip 10/100 Ethernet

Controller with HP Auto-MDIX

PRODUCT FEATURES

Highlights

Optimized for medium to high performance

applications

Efficient architecture with low CPU overhead

Easily interfaces to most 16-bit embedded CPU’s

Integrated PHY with HP Auto-MDIX

Supports audio & video streaming over Ethernet:

1-2 high-definition (HD) MPEG2 streams

Compatible with other members of LAN9218 family

Reduced Power Modes

—

Numerous power management modes

Wake on LAN*

Magic packet wakeup*

Wakeup indicator event signal

Link Status Change

Datasheet

Single chip Ethernet controller

Fully compliant with IEEE 802.3/802.3u standards

Integrated Ethernet MAC and PHY

10BASE-T and 100BASE-TX support

Full- and Half-duplex support

Full-duplex flow control

Backpressure for half-duplex flow control

Preamble generation and removal

Automatic 32-bit CRC generation and checking

Automatic payload padding and pad removal

Loop-back modes

One 48-bit perfect address

64 hash-filtered multicast addresses

Pass all multicast

Promiscuous mode

Inverse filtering

Pass all incoming with status report

Disable reception of broadcast packets

Target Applications

Video distribution systems, multi-room PVR

Cable, satellite, and IP set-top boxes

Digital video recorders and DVD recorder/players

High definition televisions

Digital media clients/servers and home gateways

Video-over IP Solutions, IP PBX & video phones

Wireless routers & access points

High-end audio distribution systems

Flexible address filtering modes

Key Benefits

Non-PCI Ethernet controller for medium-high

performance applications

—

Highest performing non-PCI Ethernet controller

16-bit interface with fast bus cycle times

Burst-mode read support

External MII Interface

Integrated 10/100 Ethernet PHY

— Supports HP Auto-MDIX

— Auto-negotiation

— Supports energy-detect power down

High-Performance host bus interface

—

Simple, SRAM-like interface

16-bit data bus

16Kbyte FIFO with flexible TX/RX allocation

One configurable host interrupt

Low-profile, green, lead-free 100-pin TQFP package

Integrated 1.8V regulator

General Purpose Timer

Optional EEPROM interface

Support for 3 status LEDs multiplexed with

Programmable GPIO signals

Eliminates dropped packets

— Internal buffer memory can store over 200 packets

— Automatic PAUSE and back-pressure flow control

Miscellaneous features

Minimizes CPU overhead

— Supports Slave-DMA

— Interrupt Pin with Programmable Hold-off timer

Reduces system cost and increases design flexibility

SRAM-like interface easily interfaces to most

embedded CPU’s or SoC’s

Single 3.3V Power Supply with 5V tolerant I/O

0 to 70°C Commercial Temperature Support

Third-party brands and names are the property of their respective

owners.

SMSC LAN9217

DATASHEET

Revision 1.5 (07-18-06)

16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX

Datasheet

ORDER NUMBERS:

LAN9217-MT FOR GREEN, LEAD-FREE, 100-PIN, TQFP PACKAGE WITH E3 FINISH (MATTE TIN)

LAN9217-MT-E2 FOR GREEN, LEAD-FREE, 100-PIN, TQFP PACKAGE WITH E2 FINISH (TIN-COPPER)

80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123

Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for

construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC

reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications

before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent

rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated

version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors

known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not

designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property

damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of

this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered

trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.

SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY,

FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE

OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL

DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT;

TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD

TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

Revision 1.5 (07-18-06)

DATASHEET

SMSC LAN9217

16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX

Datasheet

Table of Contents

Chapter 1

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

1.10

1.11

1.12

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Compatibility with First-generation LAN9118 Family Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Internal Block Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10/100 Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10/100 Ethernet MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Receive and Transmit FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GPIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Serial EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Management Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

General Purpose Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Host Bus Interface (SRAM Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

External MII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 2 Pin Description and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.1

Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Chapter 3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.1

3.2

10/100 Ethernet MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.1

Full-Duplex Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.2

Half-Duplex Flow Control (Backpressure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.3

Virtual Local Area Network (VLAN) Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Address Filtering Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Filtering Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.1

Perfect Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.2

Hash Only Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Wake-up Frame Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.1

Magic Packet Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Host Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6.1

Bus Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6.2

Bus Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Big and Little Endian Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Word Swap Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

General Purpose Timer (GP Timer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.10.1 MAC Address Auto-Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.10.2 EEPROM Host Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.11.1 System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.11.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.11.3 Internal PHY Power-Down modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Detailed Reset Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.12.1 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.12.2 Hardware Reset Input (nRESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.12.3 Resume Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.12.4 Soft Reset (SRST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.12.5 PHY Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MII Interface - External MII Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.13.1 SMI Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.13.2 MII Clock Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3

3.4

3.5

3.6

3.7

3.8

3.9

3.10

3.11

3.12

3.13

SMSC LAN9217

DATASHEET

Revision 1.5 (07-18-06)

16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX

Datasheet

3.14

3.15

TX Data Path Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.14.1 TX Buffer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.14.2 TX Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.14.3 TX Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.14.4 TX Status Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.14.5 Calculating Actual TX Data FIFO Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.14.6 Transmit Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.14.7 TX Data FIFO Underrun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.14.8 Transmitter Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.14.9 Stopping and Starting the Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

RX Data Path Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.15.1 RX Slave PIO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.15.2 RX Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.15.3 The LAN9217 host bus interface supports 16-bit bus transfers; internally, all data paths are

32-bits wide.

Figure 3.18

describes the host read ordering for pairs of atomic 16-bit trans-

actions.RX Status Format58

3.15.4 Stopping and Starting the Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.15.5 Receiver Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Chapter 4 Internal Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

4.1

4.2

Top Level Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

100Base-TX Transmit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.1

4B/5B Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.2

Scrambling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.3

NRZI and MLT3 Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.4

100M Transmit Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.5

100M Phase Lock Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

100Base-TX Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.1

100M Receive Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.2

Equalizer, Baseline Wander Correction and Clock and Data Recovery . . . . . . . . . . . . .

4.3.3

NRZI and MLT-3 Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.4

Descrambling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.5

Alignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.6

5B/4B Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10Base-T Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4.1

10M Transmit Data across the internal MII bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4.2

Manchester Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4.3

10M Transmit Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10Base-T Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5.1

10M Receive Input and Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5.2

Manchester Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5.3

Jabber Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Parallel Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.7.1

Re-starting Auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.7.2

Disabling Auto-negotiation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.7.3

Half vs. Full-Duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

HP Auto-MDIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3

4.4

4.5

4.6

4.7

4.8

Chapter 5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

5.1

5.2

Register Nomenclature and Access Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RX and TX FIFO Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2.1

RX FIFO Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2.2

TX FIFO Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Revision 1.5 (07-18-06)

DATASHEET

SMSC LAN9217

16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX

Datasheet

5.3

5.4

5.5

System Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

5.3.1

ID_REV—Chip ID and Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

5.3.2

IRQ_CFG—Interrupt Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

5.3.3

INT_STS—Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

5.3.4

INT_EN—Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

5.3.5

BYTE_TEST—Byte Order Test Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

5.3.6

FIFO_INT—FIFO Level Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

5.3.7

RX_CFG—Receive Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

5.3.8

TX_CFG—Transmit Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

5.3.9

HW_CFG—Hardware Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

5.3.10 RX_DP_CTRL—Receive Datapath Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

5.3.11 RX_FIFO_INF—Receive FIFO Information Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

5.3.12 TX_FIFO_INF—Transmit FIFO Information Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

5.3.13 PMT_CTRL— Power Management Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

5.3.14 GPIO_CFG—General Purpose IO Configuration Register . . . . . . . . . . . . . . . . . . . . . . . 88

5.3.15 GPT_CFG-General Purpose Timer Configuration Register . . . . . . . . . . . . . . . . . . . . . . 89

5.3.16 GPT_CNT-General Purpose Timer Current Count Register . . . . . . . . . . . . . . . . . . . . . . 90

5.3.17 WORD SWAP—Word Swap Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

5.3.18 FREE_RUN—Free-Run 25MHz Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

5.3.19 RX_DROP– Receiver Dropped Frames Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

5.3.20 MAC_CSR_CMD – MAC CSR Synchronizer Command Register . . . . . . . . . . . . . . . . . 92

5.3.21 MAC_CSR_DATA – MAC CSR Synchronizer Data Register . . . . . . . . . . . . . . . . . . . . . 92

5.3.22 AFC_CFG – Automatic Flow Control Configuration Register . . . . . . . . . . . . . . . . . . . . . 93

5.3.23 E2P_CMD – EEPROM Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

5.3.24 E2P_DATA – EEPROM Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

MAC Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

5.4.1

MAC_CR—MAC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

5.4.2

ADDRH—MAC Address High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

5.4.3

ADDRL—MAC Address Low Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

5.4.4

HASHH—Multicast Hash Table High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

5.4.5

HASHL—Multicast Hash Table Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

5.4.6

MII_ACC—MII Access Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

5.4.7

MII_DATA—MII Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

5.4.8

FLOW—Flow Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

5.4.9

VLAN1—VLAN1 Tag Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

5.4.10 VLAN2—VLAN2 Tag Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

5.4.11 WUFF—Wake-up Frame Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

5.4.12 WUCSR—Wake-up Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

PHY Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

5.5.1

Basic Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

5.5.2

Basic Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

5.5.3

PHY Identifier 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

5.5.4

PHY Identifier 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

5.5.5

Auto-negotiation Advertisement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

5.5.6

Auto-negotiation Link Partner Ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

5.5.7

Auto-negotiation Expansion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

5.5.8

Mode Control/Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

5.5.9

Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

5.5.10 Special Control/Status Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

5.5.11 Interrupt Source Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

5.5.12 Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

5.5.13 PHY Special Control/Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Chapter 6 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

6.1

Host Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

SMSC LAN9217

Revision 1.5 (07-18-06)

DATASHEET

LAN9217-MT Related Products

	LAN9217-MT	LAN9217	LAN9217-MT-E2
Description	1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100	1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100	1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
Address bus width	7	7	7
External data bus width	16	16	16
low power mode	YES	Yes	YES
Number of terminals	100	100	100
Maximum operating temperature	70 °C	70 Cel	70 °C
surface mount	YES	Yes	YES
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	GULL WING	GULL WING	GULL WING
Terminal location	QUAD	Four	QUAD
Maker	SMSC	-	SMSC
Parts packaging code	QFP	-	QFP
package instruction	LFQFP,	-	LFQFP,
Contacts	100	-	100
Reach Compliance Code	unknow	-	unknow
boundary scan	NO	-	NO
maximum clock frequency	25 MHz	-	25 MHz
Data encoding/decoding methods	NRZI; BIPH-LEVEL(MANCHESTER)	-	NRZI; BIPH-LEVEL(MANCHESTER)
Maximum data transfer rate	12.5 MBps	-	12.5 MBps
JESD-30 code	S-PQFP-G100	-	S-PQFP-G100
JESD-609 code	e3	-	e2
length	14 mm	-	14 mm
Number of serial I/Os	1	-	1
Package body material	PLASTIC/EPOXY	-	PLASTIC/EPOXY
encapsulated code	LFQFP	-	LFQFP
Package shape	SQUARE	-	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH	-	FLATPACK, LOW PROFILE, FINE PITCH
Certification status	Not Qualified	-	Not Qualified
Maximum seat height	1.6 mm	-	1.6 mm
Maximum supply voltage	3.63 V	-	3.63 V
Minimum supply voltage	2.97 V	-	2.97 V
Nominal supply voltage	1.8 V	-	3.3 V
technology	CMOS	-	CMOS
Terminal surface	MATTE TIN	-	TIN COPPER
Terminal pitch	0.5 mm	-	0.5 mm
width	14 mm	-	14 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, LAN	-	SERIAL IO/COMMUNICATION CONTROLLER, LAN

Recommended Resources

Typical air conditioner remote control transmission circuit schematic diagram (Hisense air conditioner)

The structure and working principle diagram of various protection circuits b

M50194AP application circuit

Sound and light controlled intelligent switch circuit

Fast grating circuit

Use used car spark plugs to realize water level control circuit

About the keyboard display problem of 51 single chip microcomputer: #include"display.h" #include"keyscan.h" #include"12864.h" #include"delay.h" void display(void) { unsigned char x,y,a,first,end; unsigned char n = 0 ; int i; for( i=0;i=0)&&(a1) { first = first*10 + a;...; 暮日落流年 51mcu

Can any kind person send me a schematic diagram of the minimum FPGA system (FPGA chip is preferably Altera's cyclone series...: Could any kindhearted person send me a schematic diagram of the minimum FPGA system (FPGA chip is preferably Altera's cyclone series)... Urgent! Urgent! Please send it to my email address [email]69218...; daifuqiang FPGA/CPLD

After turning off the PWM clock pulse, is the output state of the PWM determined?: The C2000 PWM has a clock control register that can turn on or off the PWM clock: SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Enable TBCLK within the EPWM This turns on the clock. When the PWM is workin...; dontium Microcontroller MCU

[Original] Comparison of SDK programming frameworks between VC6 and eVC4: In the VC6 IDE, use the Visual Assistant's Win32 Standard application template and write a class name, such as "myclass", and it will compile and run normally: [code]#include LRESULT CALLBACK WndProc ...; 羽灵 Embedded System

What does error A17: INVALID BYTE BASE IN BIT ADDRESS EXPRESSION mean?: My program gets the above error when compiling: invalid number of bytes based on bit address overflow? Is this what it means?...; zhazhyrjkf3 Embedded System

Q2406B's built-in TCP protocol stack: Why can't my Q2406B input its own TCP/IP protocol stack in the HyperTerminal? For example, AT#CONNECTIONSTART. I just started to study it and don't know how to do it. Please give me some advice....; niyongqiao Embedded System

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components