NWK914D
NWK914D
PHY/PMD High Speed Copper Media Transceiver
Preliminary Information
DS4829 - 1.1 December 1997
The NWK914D is a Physical Layer device designed for
use in 100BASE-TX applications. The NWK914D has
integrated the 100mb/s transceiver, clock and data recovery
and NRZI conversion circuitry. It is designed for use in cost
effective NIC adapter cards and 100BASE-TX repeater and
switch applications.
The device connects through a 5 bit symbol interface
directly with any MAC controller that includes the PCS layer,
resulting in a simple and cost effective solution. It will also
interface with a PCS device such as the NWK935 to form a
complete 100BASE-TX Physical Layer for connection to the
IEEE 802.3 standard MII interface.
RDAT4
RDAT3
RDAT2
RDAT1
RDAT0
TXC
TTLV
CC
REFCLK
TDAT0
TDAT1
TDAT2
TDAT3
52
51
50
49
48
47
46
45
44
43
42
41
40
TDAT4
TTLGND
N/C
N/C
RXC
SDT
RDLV
CC
N/C
N/C
RXPLLGND
LFRB
LFRA
RXPLLV
CC
RXV
CC
FEATURES
s
Compatible with IEEE-802.3 Standards
s
Operates over 100 Meters of STP and Category 5
UTP cable
s
Five Bit TTL Level Symbol Interface
s
Integrated Clock and Data Recovery
s
Supports Full-duplex Operation
s
Integral 10 Mb/s Buffer for Dual 10 Mb/s & 100 Mb/s
Applications
s
Adaptive Equalization
s
25MHz to 125MHz Transmit Clock Multiplier
s
Programmable TX Output Current
s
Base Line Wander Correction
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
TTLGND
TEST
TESTIP
N10/100
LBEN
TDLV
CC
TXOE
TXPLLV
CC
LFTA
LFTB
TXPLLGND
BGAPGND
SUBGND
RXGND
RXIP
RXIN
RXV
CC
1
EQSEL
10TXIN
10TXIP
TXV
CC
TXON
TXOP
TXGND
TXREF
BGAPV
CC
14
15
16
17
18
19
20
21
22
23
24
25
26
GP52
Fig.1 Pin connections - top view
s
Single +5V supply
s
52 Pin PQFP package
ORDERING INFORMATION
NWK914D/CG/GP1N
MAC or
Repeater
Controller
IC
MII
Interface
Symbol
Interface
NWK935
100 PCS
NWK914D
Isolation
Magnetics
RJ-45
Fig.2 Simplified system diagram
1
NWK914D
ABSOLUTE MAXIMUM RATINGS
Operation at absolute maximum ratings is not implied.
Exposure to stresses outside those listed could cause
permanent damage to the device.
DC Supply voltage (V
CC
)
Storage temperature (tst)
ESD
-0.5 to +7V
-65 to +150°C
2kV HBM
RECOMMENDED OPERATING CONDITIONS
DC supply voltages (V
CC
)
+5V
±5%
Operating temperature (T
A
) 0°C to +70°C (+25°C typ.)
750mW (typ.)
Power dissipation (P
D
)
ELECTRICAL CHARACTERISTICS
Recommended operating conditions apply except where stated.
Characteristic
DC characteristics
Total V
CC
supply current
TTL high level I/P voltage
TTL low level I/P voltage
TTL high level I/P current
TTL low level I/P current
EQSEL high level I/P voltage
EQSEL low level I/P voltage
EQSEL floating level I/P
EQSEL high level I/P current
EQSEL low level I/P current
TTL high level O/P voltage
TTL low level O/P voltage
TTL high level O/P current
TTL low level O/P current
Transmit O/P current
pins TXOP, TXON
Differential RX I/P
signal voltage
RX I/P common mode voltage
RX I/P impedance
Signal detect threshold
Low voltage shutdown
PLL characteristics
3dB bandwidth
Damping factor
Peaking
Overshoot
Static error
Jitter
VCO characteristics
Centre frequency
Deviation
Gain
@125MHz
-
-
-
±40
70
125
-
-
-
MHz
MHz/V
MHz
-
-
-
-
-
-
50
2
-
-
±0.5
-
-
-
.005
5
-
0.5
dB
%
ns
ns
kHz
V
TH
-
-
I
CC
V
IH
V
IL
I
IH
I
IL
V
IH
V
IL
V
IZ
I
IH
I
IL
V
OH
V
OL
I
OH
I
OL
-
2
-
-
-
4.2
-
-
-
-
2.4
-
-
-
-
-
-
150
-
-
-
-
-
-
V
CC
/2
-
-
-
-
-
-
40
1.4
V
CC
/2
-
50
3.8
-
-
0.8
20
–400
-
0.8
-
1400
–1400
-
0.5
–200
4
-
-
-
24
-
-
mA
V
V
µA
µA
V
V
V
µA
µA
V
V
µA
mA
mA
Vp-p
V
-
%
V
R
REF
= 1300Ω
100Mb/s data
measured on device pins
100Mb/s data, 0mCable
RX I/Ps floating
kΩ
wrt normalized output of
equalizer
V
IH
= V
CC
V
IL
= 0V
I
OH
= 20µA
I
OL
= 4mA
device only
V
IH
= V
CC
V
IL
= 0.4V
Symbol
Min.
Value
Typ.
Max.
Units
Conditions
2
NWK914D
TTLV
CC
LFTA
LFTB
RXPLLV
CC
TXPLLV
CC
TXOE
TXREF
10T
X
IN
10T
X
IP
TDLV
CC
N10/100
RDLV
CC
REFCLK
TXC
TDAT0
TDAT1
TDA
T2
TDAT3
TDAT4
BGAPV
CC
BGAPGND
RXC
RDAT0
RDAT1
RDAT2
RDAT3
RDA
T4
TIMES FIVE
CLOCK
MULTIPLIER
125
MHz
LOW VOLTAGE
SHUT DOWN
CURRENT
REFERENCE
10
Mb/s
TXV
CC
SHIFTER &
NRZ to NRZI
B AND GAP
VOLTAGE
REFERENCE
NRZI
to
MLT-3
100
Mb/s
TXOP
TXON
TXGND
DIVIDE
CLOCK
by FIVE
CLOCK
RECOVERY
PLL,125MHZ
TTL
3
LEVEL
LBEN
SHIFTER &
NRZI to NRZ
COMPARATORS
MLT-3 to NRZI
ADAPTIVE
EQUALIZER
EQSEL
RXIP
RXIN
RXV
CC
2
TTL
SIGNAL
DETECT
RXV
CC
1
RXGND
SUBGND
TTLGND1 TTLGND2
LFRA
LFRB
SDT
RXPLLGND TXPLLGND TESTIP
TEST
Fig.3 System block diagram
FUNCTIONAL DESCRIPTION
The functional blocks within the device are shown in Fig. 3.
These are described below:-
NRZ to MLT3 Encoder
The serial data from the shifter then passes through an
encoder which converts the NRZI binary data into the three
level MLT-3 format for transmission by the 'TXO' outputs.
Transmit Line Drivers
There are two on-chip Line Drivers both of which share
the output pins TXOP and TXON. The N10/100 pin is used
to control which driver is active and allowed to drive the line.
When held high the MLT-3 data is output by the 100Mb/s
driver. This driver consists of differential current source
outputs with programmable sink capability, designed to
drive a nominal output impedance of 50Ω.
Output current is set by the value of an external resistor
(R
REF
) between pin 'TXREF' and 'TXGND'.
This resistor defines an internal reference current derived
from an on-chip bandgap reference.
Final output current at the 'TXO' outputs is a multiple of
this current and is defined as:-
I
TXO
(mA)
Transmit Section
Times Five Clock Multiplier 25MHz to 125MHz
This circuit consists of a phase lock loop (PLL) that is
operating at 125MHz, centre frequency. The 125MHz is
divided by 5 to produce a 25MHz clock which is phase
compared with a 25MHz crystal clock reference frequency
which is input on pin REFCLK. The 25MHz clock (pin TXC)
is then sent to the PCS layer to clock in in the 5 bit nibble
data. Pins LFTA and LFTB are provided to set the VCO
characteristics. The recommended loop filter components
are shown in Fig.6.
A control current is derived from the clock multiplier and
is used by the receive clock recovery circuit to centre the
PLL when no input data is present.
Five Bit Nibble to 125MHz Shifter
Data is input to the transmit side in 5 bit wide parallel
form on pins TDAT0 through TDAT4. This NRZ data is
clocked in on the positive edge of the 25MHz clock pin TXC.
The parallel data is first loaded into a 5 bit wide register prior
to being loaded into a 5 bit PISO where it is converted into
a serial data stream. The last stage of the shifter incorporates
a converter to change the data from NRZ to NRZI.
= 52/R
REF
(kΩ)
Transition times of the 'TXO' outputs are matched and
internally limited to approx. 2.5ns to reduce EMI emissions.
3
NWK914D
When N10/100 is held low the 10Mb/s driver is selected.
This 10Mb/s driver consists of a differential analog buffer
designed to take a fully cable conditioned 10Mb/s signal
from the filter output of existing 10BASE-T electronics. The
10BASE-T signal is input on pins 10TXIN and 10TXIP. The
output current of the buffer is determined by the same
external R
REF
resistor on pin TXREF as used for the 100Mb/
s driver.
The unselected driver is switched to a tristated power
save mode. A low voltage shutdown circuit turns off both TX
drivers when V
CC
voltage falls to a level below the specified
minimum.
When operating in single 100Mb/s applications a 1:1
turn ratio magnetics will be used and therefore to attain the
desired line driving current of 40mA out of the secondary a
TXO output drive of 40mA is required. Using the above
formula it will be found that 1.3Ω is the nearest prefered
value to that required to give the 40mA.
In the case of dual 10Mb/s and 100Mb/s applications a
2:1 turn ratio magnetics is recommended. The use of 2:1
magnetics enables a greater efficiency to be gained from
the 10Mb/s driver by using a lower output current. At the
same time this lower current is also true of the 100Mb/s
output where now only a 20mA drive is required. An R
REF
value of 2.6KΩ is used to set this current. Internal current
ratioing within the device will ensure that the correct drive
current is chosen depending upon whether the drives are in
10Mb/s or 100Mb/s mode as selected by pin N10/100.
The R
REF
value can be adjusted to compensate for
different magnetics and board layouts. The object is to
achieve an output level of 2V p-p measured at the RJ45
socket in compliance with 802.3.
When the TXOE pin is held low the TXdrivers are tri-
stated regardless of the mode selected by the N10/100 pin.
Base Line Wander Correction
MLT-3 codes have significant low frequency components
in their spectrum which are not transmitted through the
transformers that couple the line to the board. This results in
'Base Line Wander', which can significantly reduce the
noise immunity of the receiver.
The purpose ot the correction circuit is to restore these
low frequency components through the use of a feedback
arrangement. The circuit will also correct any DC offset that
may exist on the receive signal.
Signal Detector
A signal detect circuit is provided which continuously
monitors the amplitude of the input signal being received on
pins RXIP and RXIN. After the input signal reaches the
specified level which the equalizer can correctly equalize,
SDT is asserted high. Conversely if the signal level falls
below a limit for reliable operation then SDT will go low.
Comparators MLT-3 to NRZ Decoder
The equalized MLT-3 data is then passed to a set of
window comparators which are used to determine the signal
level. The comparator outputs are OR’ed together to
reconstitute the NRZI data.
PLL Clock Recovery
This function consists of a 125MHz PLL that is locked to
the incoming data stream. The PLL is first centred to the
transmit clock multiplier using an internal analog reference
signal. Once a valid input signal is present, the PLL will lock
to, and thus extract the clock from, the incoming data
stream. Pins LFRA and LFRB are provided to set the VCO
characteristics. The recommended loop filter components
are shown in Fig.6.
125MHz Shifter to Parallel Data
The 125Mb/s serial data stream with an accompanying
phase related 125MHz clock is output from the PLL.
This data stream is clocked into the serial to parallel
register using the 125MHz clock. This data is then latched
prior to being clocked out on pins RDAT0 to RDAT4. A
25MHz clock, derived from the 125MHz PLL by a divide by
5, is used to clock the parallel data and is output to pin RXC.
Loopback Logic
Pin ‘LBEN’ controls loopback operation. A low level on
this pin defines normal operation, a high level defines
loopback mode. In loopback mode, the transmit data is
internally routed to the receive circuitry, SDT is forced high
and the TXOP and TXON outputs are disabled.
Test Pins and No-Connects
Two pins are provided on the product to aid testing in
production. These pins TEST(38), and TESTIP(37) must be
left unconnected for normal operation in application circuits.
Additionally, there are four No-Connect pins (2,3,7,8)
which also mustt be left unconnected for normal operation.
Receiver Section
Equalizer
The equalizer circuit is necessary to compensate for
signal degradation due to cable losses, however over-
equalization must be avoided to prevent excessive overshoots
resulting in errors during the reception of MLT-3 data. Three
operating modes are therefore provided.
These three operating modes are controlled by the state
of tristate input 'EQSEL' and are described below:-
1) Auto Equalization ('EQSEL' floating)
Fully automatic equalization is achieved through the
use of a feedback loop driven by a control signal derived
from the signal amplitude. This provides adaptive control
and prevents over-modulation of the signal when short
cable lengths are used.
2) Full Equalization ('EQSEL' low)
In this mode, full equalization is applied to the input
signal irrespective of amplitude.
3) No Equalization ('EQSEL high)
The equalization circuit is disabled completely during
this mode.
4
Embedded System
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