MC74AC374, MC74ACT374
Octal D-Type Flip-Flop with
3-State Outputs
The MC74AC374/74ACT374 is a high−speed, low−power octal
D−type flip−flop featuring separate D−type inputs for each flip−flop
and 3−state outputs for bus−oriented applications. A buffered Clock
(CP) and Output Enable (OE) are common to all flip−flops.
Features
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•
•
•
•
•
•
•
•
Buffered Positive Edge−Triggered Clock
3−State Outputs for Bus−Oriented Applications
Outputs Source/Sink 24 mA
See MC74AC273 for Reset Version
See MC74AC377 for Clock Enable Version
See MC74AC373 for Transparent Latch Version
See MC74AC574 for Broadside Pinout Version
See MC74AC564 for Broadside Pinout Version with Inverted
Outputs
•
′ACT374
Has TTL Compatible Inputs
•
These are Pb−Free Devices
SOIC−20W
DW SUFFIX
CASE 751D
1
TSSOP−20
DT SUFFIX
CASE 948E
1
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 6 of this data sheet.
V
CC
20
O
7
19
D
7
18
D
6
17
O
6
16
O
5
15
D
5
14
D
4
13
O
4
12
CP
11
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
1
OE
2
O
0
3
D
0
4
D
1
5
O
1
6
O
2
7
D
2
8
D
3
9
O
3
10
GND
Figure 1. Pinout: 20 Lead Packages Conductors
(Top View)
PIN ASSIGNMENT
PIN
D
0
−D
7
CP
OE
O
0
−O
7
FUNCTION
Data Inputs
Clock Pulse Input
3−State Output Enable Input
3−State Outputs
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CP
OE
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
Figure 2. Logic Symbol
©
Semiconductor Components Industries, LLC, 2015
1
March, 2015 − Rev. 9
Publication Order Number:
MC74AC374/D
MC74AC374, MC74ACT374
TRUTH TABLE
Inputs
D
n
H
L
X
CP
OE
L
L
H
Outputs
O
n
H
L
Z
X
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
FUNCTIONAL DESCRIPTION
The MC74AC374/74ACT374 consists of eight edge−
triggered flip−flops with individual D−type inputs and
3−state true outputs. The buffered clock and buffered Output
Enable are common to all flip−flops. The eight flip−flops
will store the state of their individual D inputs that meet the
setup and hold time requirements on the LOW−to−HIGH
Clock (CP) transition. With the Output Enable (OE) LOW,
the contents of the eight flip−flops are available at the
outputs. When the OE is HIGH, the outputs go to the high
impedance state. Operation of the OE input does not affect
the state of the flip−flops.
D
0
CP
CP
Q
D
Q
CP
Q
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
Q
CP
Q
D
Q
CP
Q
D
Q
CP
Q
D
Q
CP
Q
D
Q
CP
Q
D
Q
CP
Q
D
Q
OE
O
0
NOTE:
O
1
O
2
O
3
O
4
O
5
O
6
O
7
That this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
Figure 3. Logic Diagram
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MC74AC374, MC74ACT374
MAXIMUM RATINGS
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
I
CC
I
GND
T
STG
T
L
T
J
q
JA
MSL
F
R
V
ESD
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND) (Note 1)
DC Input Diode Current
DC Output Diode Current
DC Output Sink/Source Current
DC Supply Current, per Output Pin
DC Ground Current, per Output Pin
Storage Temperature Range
Lead temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Thermal Resistance (Note 2)
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
Oxygen Index: 30% − 35%
Human Body Model (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
Above V
CC
and Below GND at 85_C (Note 6)
SOIC
TSSOP
Value
−0.5 to +7.0
−0.5 to V
CC
+0.5
−0.5 to V
CC
+0.5
±20
±50
±50
±50
±100
*65
to
)150
260
140
65.8
110.7
Level 1
UL 94 V−0 @ 0.125 in
> 2000
> 200
> 1000
±100
V
Unit
V
V
V
mA
mA
mA
mA
mA
_C
_C
_C
_C/W
I
Latchup
Latchup Performance
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. I
OUT
absolute maximum rating must be observed.
2. The package thermal impedance is calculated in accordance with JESD 51−7.
3. Tested to EIA/JESD22−A114−A.
4. Tested to EIA/JESD22−A115−A.
5. Tested to JESD22−C101−A.
6. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
Supply Voltage
DC Input Voltage, Output Voltage (Ref. to GND)
V
CC
@ 3.0 V
t
r
, t
f
Input Rise and Fall Time (Note 1)
′AC
Devices except Schmitt Inputs
V
CC
@ 4.5 V
V
CC
@ 5.5 V
t
r
, t
f
T
A
I
OH
I
OL
Input Rise and Fall Time (Note 2)
′ACT
Devices except Schmitt Inputs
Operating Ambient Temperature Range
Output Current − High
Output Current − Low
V
CC
@ 4.5 V
V
CC
@ 5.5 V
Parameter
′AC
′ACT
Min
2.0
4.5
0
−
−
−
−
−
−40
−
−
150
40
25
10
8.0
25
−
−
Typ
5.0
5.0
Max
6.0
5.5
V
CC
−
−
−
−
−
85
−24
24
ns/V
°C
mA
mA
ns/V
V
V
Unit
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
1. V
IN
from 30% to 70% V
CC
; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. V
IN
from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
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MC74AC374, MC74ACT374
DC CHARACTERISTICS
74AC
Symbol
Parameter
V
CC
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
V
OL
Maximum Low Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
I
IN
I
OZ
Maximum Input
Leakage Current
Maximum
3-State
Current
†Minimum Dynamic
Output Current
5.5
T
A
= +25°C
Typ
V
IH
Minimum High Level
Input Voltage
Maximum Low Level
Input Voltage
Minimum High Level
Output Voltage
1.5
2.25
2.75
1.5
2.25
2.75
2.99
4.49
5.49
−
−
−
0.002
0.001
0.001
−
−
−
−
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.56
3.86
4.86
0.1
0.1
0.1
0.36
0.36
0.36
±0.1
74AC
T
A
= −40°C to +85°C
Guaranteed Limits
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.46
3.76
4.76
0.1
0.1
0.1
0.44
0.44
0.44
±1.0
V
V
OUT
= 0.1 V
or V
CC
− 0.1 V
V
OUT
= 0.1 V
or V
CC
− 0.1 V
I
OUT
= −50
mA
V
*V
IN
= V
IL
or V
IH
−12 mA
I
OH
−24 mA
−24 mA
I
OUT
= 50
mA
V
*V
IN
= V
IL
or V
IH
12 mA
I
OL
24 mA
24 mA
V
I
= V
CC
, GND
V
I
(OE) = V
IL
, V
IH
V
I
= V
CC
, GND
V
O
= V
CC
, GND
V
OLD
= 1.65 V Max
V
OHD
= 3.85 V Min
V
IN
= V
CC
or GND
Unit
Conditions
V
IL
V
V
OH
V
V
mA
5.5
5.5
5.5
−
−
−
±0.5
−
−
±5.0
75
−75
mA
mA
mA
mA
I
OLD
I
OHD
I
CC
Maximum Quiescent Supply Current
5.5
−
8.0
80
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
NOTE: I
IN
and I
CC
@ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V V
CC
.
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4
MC74AC374, MC74ACT374
AC CHARACTERISTICS
(For Figures and Waveforms − See AND8277/D at www.onsemi.com)
74AC
Symbol
Parameter
V
CC
*
(V)
Min
f
max
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Maximum Clock
Frequency
Propagation Delay
CP to O
n
Propagation Delay
CP to O
n
Output Enable Time
Output Enable Time
Output Disable Time
Output Disable Time
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
60
100
3.0
2.5
2.5
2.0
3.0
2.0
2.5
2.0
3.0
2.0
2.0
1.5
T
A
= +25°C
C
L
= 50 pF
Typ
110
155
11
8.0
10
7.0
9.5
7.0
9.0
6.5
10.5
8.0
8.0
6.5
Max
−
−
13.5
9.5
12.5
9.0
11.5
8.5
11.5
8.5
12.5
11
11.5
8.5
74AC
T
A
= −40°C
to +85°C
C
L
= 50 pF
Min
60
100
1.5
1.5
2.0
1.5
1.5
1.0
1.5
1.0
2.0
2.0
1.0
1.0
Max
−
−
15.5
10.5
14
10
13
9.5
13
9.5
14.5
12.5
12.5
10
MHz
ns
ns
ns
ns
ns
ns
3−3
3−6
3−6
3−7
3−8
3−7
3−8
Unit
Fig.
No.
*Voltage Range 3.3 V is 3.3 V
±0.3
V.
Voltage Range 5.0 V is 5.0 V
±0.5
V.
AC OPERATING REQUIREMENTS
74AC
Symbol
Parameter
V
CC
*
(V)
Typ
t
s
t
h
t
w
Setup Time, HIGH or LOW
D
n
to CP
Hold Time, HIGH or LOW
D
n
to CP
3.3
5.0
3.3
5.0
3.3
5.0
2.0
1.0
−1.0
0
4.0
2.5
T
A
= +25°C
C
L
= 50 pF
74AC
T
A
= −40°C
to +85°C
C
L
= 50 pF
Unit
Fig.
No.
Guaranteed Minimum
5.5
4.0
1.0
1.5
5.5
4.0
6.0
4.5
1.0
1.5
6.0
4.5
ns
ns
ns
3−9
3−9
3−6
CP Pulse Width
HIGH or LOW
*Voltage Range 3.3 V is 3.3 V
±0.3
V.
Voltage Range 5.0 V is 5.0 V
±0.5
V.
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