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CD4050BC

Description
4000/14000/40000 SERIES, HEX 1-INPUT INVERT GATE, PDSO16
Categorysemiconductor    logic   
File Size70KB,7 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Download Datasheet Parametric Compare View All

CD4050BC Overview

4000/14000/40000 SERIES, HEX 1-INPUT INVERT GATE, PDSO16

CD4050BC Parametric

Parameter NameAttribute value
Number of functions6
Number of terminals16
Maximum operating temperature85 Cel
Minimum operating temperature-40 Cel
Maximum supply/operating voltage15 V
Minimum supply/operating voltage3 V
Rated supply voltage5 V
Processing package descriptionPlastic, SO-16
stateTRANSFERRED
CraftsmanshipCMOS
packaging shapeRectangle
Package SizeSMALL OUTLINE
surface mountYes
Terminal formGULL WING
Terminal spacing1.27 mm
Terminal locationpair
Packaging MaterialsPlastic/Epoxy
Temperature levelINDUSTRIAL
series4000/14000/40000
Logic IC typeNo
Number of inputs1
propagation delay TPD65 ns
CD4049UBC • CD4050BC Hex Inverting Buffer • Hex Non-Inverting Buffer
October 1987
Revised April 2002
CD4049UBC • CD4050BC
Hex Inverting Buffer •
Hex Non-Inverting Buffer
General Description
The CD4049UBC and CD4050BC hex buffers are mono-
lithic complementary MOS (CMOS) integrated circuits con-
structed with N- and P-channel enhancement mode
transistors. These devices feature logic level conversion
using only one supply voltage (V
DD
). The input signal high
level (V
IH
) can exceed the V
DD
supply voltage when these
devices are used for logic level conversions. These
devices are intended for use as hex buffers, CMOS to DTL/
TTL converters, or as CMOS current drivers, and at V
DD
=
5.0V, they can drive directly two DTL/TTL loads over the
full operating temperature range.
Features
s
Wide supply voltage range:
3.0V to 15V
s
Direct drive to 2 TTL loads at 5.0V over full temperature
range
s
High source and sink current capability
s
Special input protection permits input voltages greater
than V
DD
Applications
• CMOS hex inverter/buffer
• CMOS to DTL/TTL hex converter
• CMOS current “sink” or “source” driver
• CMOS HIGH-to-LOW logic level converter
Ordering Code:
Order Number
CD4049UBCM
CD4049UBCN
CD4050BCM
CD4050BCN
Package Number
M16A
N16E
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP
CD4049UBC
CD4050BC
Top View
Top View
© 2002 Fairchild Semiconductor Corporation
DS005971
www.fairchildsemi.com

CD4050BC Related Products

CD4050BC CD4049UBC CD4049UBC_02 CD4049UBCN
Description 4000/14000/40000 SERIES, HEX 1-INPUT INVERT GATE, PDSO16 4000/14000/40000 SERIES, HEX 1-INPUT INVERT GATE, PDSO16 4000/14000/40000 SERIES, HEX 1-INPUT INVERT GATE, PDSO16 4000/14000/40000 SERIES, HEX 1-INPUT INVERT GATE, PDIP16
Number of functions 6 6 6 6
Number of terminals 16 16 16 16
Maximum operating temperature 85 Cel 85 Cel 85 Cel 125 °C
Minimum operating temperature -40 Cel -40 Cel -40 Cel -55 °C
surface mount Yes Yes Yes NO
Terminal form GULL WING GULL WING GULL WING THROUGH-HOLE
Terminal location pair pair pair DUAL
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL MILITARY
series 4000/14000/40000 4000/14000/40000 4000/14000/40000 4000/14000/40000
Maximum supply/operating voltage 15 V 15 V 15 V -
Minimum supply/operating voltage 3 V 3 V 3 V -
Rated supply voltage 5 V 5 V 5 V -
Processing package description Plastic, SO-16 Plastic, SO-16 Plastic, SO-16 -
state TRANSFERRED TRANSFERRED TRANSFERRED -
Craftsmanship CMOS CMOS CMOS -
packaging shape Rectangle Rectangle Rectangle -
Package Size SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE -
Terminal spacing 1.27 mm 1.27 mm 1.27 mm -
Packaging Materials Plastic/Epoxy Plastic/Epoxy Plastic/Epoxy -
Logic IC type No No No -
Number of inputs 1 1 1 -
propagation delay TPD 65 ns 65 ns 65 ns -

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