MC74LVXT4052
Analog Multiplexer/
Demultiplexer
High−Performance Silicon−Gate CMOS
The MC74LVXT4052 utilizes silicon−gate CMOS technology to
achieve fast propagation delays, low ON resistances, and low OFF
leakage currents. This analog multiplexer/demultiplexer controls
analog voltages that may vary across the complete power supply range
(from V
CC
to V
EE
).
The LVXT4052 is similar in pinout to the high−speed HC4052A
and the metal−gate MC14052B. The Channel−Select inputs determine
which one of the Analog Inputs/Outputs is to be connected, by means
of an analog switch, to the Common Output/Input. When the Enable
pin is HIGH, all analog switches are turned off.
The Channel−Select and Enable inputs are compatible with standard
TTL levels.
This device has been designed so the ON resistance (R
ON
) is more
linear over input voltage than the R
ON
of metal−gate CMOS analog
switches and High−Speed CMOS analog switches.
Features
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MARKING
DIAGRAMS
16
SOIC−16
D SUFFIX
CASE 751B
1
LVXT4052
AWLYWW
16
TSSOP−16
DT SUFFIX
CASE 948F
1
LVXT
4052
ALYW
•
•
•
•
•
•
Select Pins Compatible with TTL Levels
Fast Switching and Propagation Speeds
Low Crosstalk Between Switches
Analog Power Supply Range (V
CC
− V
EE
) =
*3.0
V to
)3.0
V
Digital (Control) Power Supply Range (V
CC
− GND) = 2.5 to 6.0 V
16
SOEIAJ−16
M SUFFIX
CASE 966
1
LVXT4052
ALYW
Improved Linearity and Lower ON Resistance Than Metal−Gate,
HSL, or VHC Counterparts
•
Low Noise
Split Supplies up to
$
3.0 V
•
Break−Before−Make Circuitry
•
Pb−Free Packages are Available*
•
Designed to Operate on a Single Supply with V
EE
= GND, or Using
A
WL or L
Y
WW or W
=
=
=
=
Assembly Location
Wafer Lot
Year
Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2005
1
March, 2005 − Rev. 4
Publication Order Number:
MC74LVXT4052/D
MC74LVXT4052
V
CC
16
X2
15
X1
14
X
13
X0
12
X3
11
A
10
B
9
FUNCTION TABLE
Control Inputs
Select
Enable
L
L
L
L
H
X = Don’t Care
B
L
L
H
H
X
A
L
H
L
H
X
ON Channels
Y0
Y1
Y2
Y3
NONE
X0
X1
X2
X3
1
Y0
2
Y2
3
Y
4
Y3
5
Y1
6
7
Enable V
EE
8
GND
Figure 1. Pin Connection and Marking Diagram
(Top View)
ANALOG
INPUTS/OUTPUTS
X0
14
X1
15
X2
11
X3
Y0
Y1
Y2
Y3
A
B
1
5
2
4
10
9
6
12
X SWITCH
13
X
COMMON
OUTPUTS/INPUTS
Y SWITCH
3
Y
CHANNEL-SELECT
INPUTS
ENABLE
PIN 16 = V
CC
PIN 7 = V
EE
PIN 8 = GND
NOTE: This device allows independent control of each switch.
Channel−Select Input A controls the X−Switch, Input B controls the Y−Switch.
Figure 2. Logic Diagram
Double−Pole, 4−Position Plus Common Off
ORDERING INFORMATION
Device
MC74LVXT4052D
MC74LVXT4052DG
MC74LVXT4052DR2
MC74LVXT4052DR2G
MC74LVXT4052DT
MC74LVXT4052DTR2
MC74LVXT4052M
MC74LVXT4052MG
MC74LVXT4052MEL
MC74LVXT4052MELG
Package
SOIC−16
SOIC−16
(Pb−Free)
SOIC−16
SOIC−16
(Pb−Free)
TSSOP−16*
TSSOP−16*
SOEIAJ−16
SOEIAJ−16
(Pb−Free)
SOEIAJ−16
SOEIAJ−16
(Pb−Free)
Shipping
†
48 Units / Rail
48 Units / Rail
2500 Tape & Reel
2500 Tape & Reel
96 Units / Rail
2500 Tape & Reel
50 Units / Rail
50 Units / Rail
2000 Tape & Reel
2000 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
MC74LVXT4052
NORMALIZED FAILURE RATE
T
J
= 130_C
T
J
= 120_C
T
J
= 90_C
80
90
100
110
120
130
140
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
117.8
47.9
20.4
9.4
4.2
2.0
1.0
1
1
10
TIME, YEARS
100
1000
Figure 3. Failure Rate vs. Time Junction Temperature
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3
T
J
= 80_C
Time, Hours
Time, Years
T
J
= 100_C
T
J
= 110_C
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MAXIMUM RATINGS
Symbol
V
EE
Parameter
Value
Unit
V
V
V
V
Negative DC Supply Voltage
Positive DC Supply Voltage
Analog Input Voltage
Digital Input Voltage
(Referenced to GND)
V
CC
V
IS
(Referenced to GND)
(Referenced to V
EE
)
*
7.0 to
)0.5
*
0.5 to
)7.0
*
0.5 to
)7.0
*
0.5 to 7.0
$20
V
EE
*
0.5 to V
CC
)0.5
V
IN
I
(Referenced to GND)
DC Current, Into or Out of Any Pin
Storage Temperature Range
mA
_C
_C
_C
T
STG
T
L
T
J
*
65 to
)150
260
)150
143
164
500
450
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature under Bias
Thermal Resistance
q
JA
P
D
SOIC
TSSOP
SOIC
TSSOP
°C/W
mW
Power Dissipation in Still Air,
Moisture Sensitivity
MSL
F
R
Level 1
Flammability Rating
Oxygen Index: 30% − 35%
UL 94−V0 @ 0.125 in
u2000
u200
u1000
$300
V
ESD
ESD Withstand Voltage
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
V
I
LATCHUP
Latchup Performance
Above V
CC
and Below GND at 125°C (Note 4)
mA
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. Tested to EIA/JESD22−A114−A.
2. Tested to EIA/JESD22−A115−A.
3. Tested to JESD22−C101−A.
4. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
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V
EE
Negative DC Supply Voltage
Positive DC Supply Voltage
Analog Input Voltage
Digital Input Voltage
(Referenced to GND)
Symbol
Parameter
Min
Max
Unit
V
V
V
V
*
6.0
2.5
2.5
GND
6.0
6.0
V
CC
V
IS
T
A
(Referenced to GND)
(Referenced to V
EE
)
V
EE
0
V
CC
6.0
125
100
20
V
IN
(Note 5) (Referenced to GND)
V
CC
= 3.0 V
$
0.3 V
V
CC
= 5.0 V
$
0.5 V
Operating Temperature Range, All Package Types
*
55
0
0
_C
t
r
, t
f
Input Rise/Fall Time
(Channel Select or Enable Inputs)
ns/V
5. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
Junction
Temperature
°C
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
MC74LVXT4052
DC CHARACTERISTICS − Digital Section
(Voltages Referenced to GND)
V
CC
V
3.0
4.5
5.5
3.0
4.5
5.5
V
IN
= 6.0 or GND
Channel Select, Enable and
V
IS
= V
CC
or GND
0 V to 6.0 V
6.0
Guaranteed Limit
*55
to 25°C
2.0
2.0
2.0
0.5
0.8
0.8
$0.1
4.0
v85°C
2.0
2.0
2.0
0.5
0.8
0.8
$1.0
40
v125°C
2.0
2.0
2.0
0.5
0.8
0.8
$1.0
80
Unit
V
Symbol
V
IH
Parameter
Minimum High−Level Input Volt-
age,
Channel−Select or Enable Inputs
Maximum Low−Level Input Volt-
age,
Channel−Select or Enable Inputs
Maximum Input Leakage Current,
Channel−Select or Enable Inputs
Maximum Quiescent Supply
Current (per Package)
Condition
V
IL
V
I
IN
I
CC
mA
mA
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Î
Î
Symbol
R
ON
Parameter
Test Conditions
V
CC
V
3.0
4.5
3.0
3.0
4.5
3.0
V
EE
V
Guaranteed Limit
v85_C
108
46
33
20
18
15
*55
to 25°C
86
37
26
15
13
10
v125_C
120
55
37
20
18
15
Unit
W
Maximum “ON” Resistance
V
IN
= V
IL
or V
IH
V
IS
=
½
(V
CC
− V
EE
)
|I
S
| = 2.0 mA (Figure 4)
V
IN
= V
IL
or V
IH
V
IS
=
½
(V
CC
− V
EE
)
|I
S
| = 2.0 mA
0
0
*
3.0
0
0
*
3.0
0
−3.0
0
−3.0
0
−3.0
DR
ON
Maximum Difference in “ON” Re-
sistance Between Any Two
Channels in the Same Package
W
I
off
Maximum Off−Channel Leakage
Current, Any One Channel
Maximum Off−Channel
Leakage Current,
Common Channel
I
on
Maximum On−Channel
Leakage Current,
Channel−to−Channel
V
in
= V
IL
or V
IH
;
V
IO
= V
CC
or GND;
Switch Off (Figure 3)
V
in
= V
IL
or V
IH
;
V
IO
= V
CC
or GND;
Switch Off (Figure 4)
V
in
= V
IL
or V
IH
;
Switch−to−Switch =
V
CC
or GND; (Figure 5)
5.5
+3.0
5.5
+3.0
5.5
+3.0
0.1
0.1
0.2
0.2
0.2
0.2
0.5
0.5
2.0
2.0
2.0
2.0
1.0
1.0
4.0
4.0
4.0
4.0
mA
mA
DC ELECTRICAL CHARACTERISTICS − Analog Section
AC CHARACTERISTICS
(Input t
r
= t
f
= 3 ns)
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Î
Guaranteed Limit
Symbol
t
BBM
Parameter
Test Conditions
V
CC
V
3.0
4.5
3.0
V
EE
V
*55
to 25_C
Min
1.0
1.0
1.0
Typ*
6.5
5.0
3.5
v85_C
−
−
−
v125_C
−
−
−
Unit
ns
Minimum Break−Before−Make
Time
V
IN
= V
IL
or V
IH
V
IS
= V
CC
R
L
= 300
W,
C
L
= 35 pF
(Figures 12 and 13)
0.0
0.0
*
3.0
*Typical Characteristics are at 25_C.
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4
MC74LVXT4052
AC CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 3 ns)
Guaranteed Limit
V
CC
V
2.5
3.0
4.5
3.0
2.5
3.0
4.5
3.0
2.5
3.0
4.5
3.0
V
EE
V
0
0
0
*
3.0
0
0
0
*
3.0
0
0
0
*
3.0
*
55 to 25°C
Min
Typ
Max
40
28
23
23
40
28
23
23
40
28
23
23
v85°C
Min
Max
45
30
25
25
45
30
25
25
45
30
25
25
v125°C
Min
Max
50
35
30
28
50
35
30
28
50
35
30
28
Unit
ns
Symbol
t
PLH
,
t
PHL
Parameter
Maximum Propagation Delay, Channel−Select
to Analog Output
(Figures 16 and 17)
Maximum Propagation Delay, Enable to Analog
Output (Figures 14 and 15)
t
PLZ
,
t
PHZ
ns
t
PZL
,
t
PZH
Maximum Propagation Delay, Enable to Analog
Output (Figures 14 and 15)
ns
Typical @ 25°C, V
CC
= 5.0 V, V
EE
= 0V
C
PD
C
IN
C
I/O
Power Dissipation Capacitance (Figure 18) (Note 6)
Maximum Input Capacitance, Channel−Select or Enable Inputs
Maximum Capacitance
(All Switches Off)
Analog I/O
Common O/I
Feedthrough
45
10
10
10
1.0
pF
pF
pF
6. Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC2
f + I
CC
V
CC
.
ADDITIONAL APPLICATION CHARACTERISTICS
(GND = 0 V)
V
CC
V
3.0
4.5
6.0
3.0
3.0
4.5
6.0
3.0
3.0
4.5
6.0
3.0
5.0
3.0
V
EE
V
0.0
0.0
0.0
*
3.0
0.0
0.0
0.0
*
3.0
0.0
0.0
0.0
*
3.0
Typ
25°C
80
80
80
80
Unit
MHz
Symbol
BW
Parameter
Maximum On−Channel Bandwidth or Minimum
Frequency Response
Condition
V
IS
=
½
(V
CC
− V
EE
)
Ref and Test Attn = 10 dB
Source Amplitude = 0 dB
(Figure 7)
f = 1 MHz; V
IS
=
½
(V
CC
− V
EE
)
Adjust Network Analyzer output to 10 dBm
on each output from the power splitter.
(Figures 8 and 9)
V
IS
=
½
(V
CC
− V
EE
)
Adjust Network Analyzer output to 10 dBm
on each output from the power splitter.
(Figure 11)
V
IN
= V
CC
to V
EE,
f
IS
= 1 kHz, t
r
= t
f
= 3 ns
R
IS
= 0
W,
C
L
= 1000 pF, Q = C
L
*
DV
OUT
(Figure 10)
f
IS
= 1 MHz, R
L
= 10 KW, C
L
= 50 pF,
V
IS
= 5.0 V
PP
sine wave
V
IS
= 6.0 V
PP
sine wave
(Figure 19)
V
ISO
Off−Channel Feedthrough Isolation
*
70
*
70
*
70
*
70
*
2
*
2
*
2
*
2
9.0
12
dB
V
ONL
Maximum Feedthrough On Loss
dB
Q
Charge Injection
*
3.0
0.0
pC
THD
Total Harmonic Distortion THD + Noise
%
6.0
3.0
0.0
*
3.0
0.10
0.05
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