ON Semiconductort
Octal Bus Buffer
Inverting
The MC74VHC540 is an advanced high speed CMOS inverting
octal bus buffer fabricated with silicon gate CMOS technology. It
achieves high speed operation similar to equivalent Bipolar Schottky
TTL while maintaining CMOS low power dissipation.
The MC74VHC540 features inputs and outputs on opposite sides of
the package and two AND- active- low output enables. When either
-ed
-
OE1 or OE2 are high, the terminal outputs are in the high impedance
state.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7V, allowing the interface of 5V systems
to 3V systems.
•
High Speed: t
PD
= 3.7ns (Typ) at V
CC
= 5V
•
Low Power Dissipation: I
CC
= 4μA (Max) at T
A
= 25°C
•
High Noise Immunity: V
NIH
= V
NIL
= 28% V
CC
•
Power Down Protection Provided on Inputs
•
Balanced Propagation Delays
•
Designed for 2V to 5.5V Operating Range
•
Low Noise: V
OLP
= 1.2V (Max)
•
Pin and Function Compatible with Other Standard Logic Families
•
Latchup Performance Exceeds 300mA
•
ESD Performance: HBM > 2000V; Machine Model > 200V
•
Chip Complexity: 124 FETs or 31 Equivalent Gates
MC74VHC540
DW SUFFIX
20--LEAD SOIC WIDE PACKAGE
CASE 751D--05
DT SUFFIX
20--LEAD TSSOP PACKAGE
CASE 948E--02
M SUFFIX
20--LEAD SOIC EIAJ PACKAGE
CASE 967--01
ORDERING INFORMATION
SOIC WIDE
MC74VHCXXXDW
TSSOP
MC74VHCXXXDT
SOIC EIAJ
MC74VHCXXXM
PIN ASSIGNMENT
OE1
A1
A2
A3
A4
A5
A6
A7
A8
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
•
These devices are available in Pb-
-free package(s). Specifications herein
apply to both standard and Pb-
-free devices. Please see our website at
www.onsemi.com for specific Pb-
-free orderable part numbers, or
contact your local ON Semiconductor sales office or representative.
FUNCTION TABLE
Inputs
OE1
L
L
H
X
OE2
L
L
X
H
A
L
H
X
X
Output Y
H
L
Z
Z
©
Semiconductor Components Industries, LLC, 2006
March, 2006 - Rev. 3
-
1
Publication Order Number:
MC74VHC540/D
LOGIC DIAGRAM
A1
A2
A3
DATA
INPUTS
A4
A5
A6
A7
A8
OUTPUT
ENABLES
OE1
OE2
2
3
4
5
6
7
8
9
1
19
18
17
16
15
14
13
12
11
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
INVERTING
OUTPUTS
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2
MAXIMUM RATINGS*
Symbol
V
CC
V
in
V
out
I
IK
I
OK
I
out
I
CC
P
D
T
stg
DC Supply Voltage
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air,
Storage Temperature
SOIC Packages†
TSSOP Package†
Parameter
Value
– 0.5 to + 7.0
– 0.5 to + 7.0
– 0.5 to V
CC
+ 0.5
-- 20
±
20
±
25
±
75
500
450
– 65 to + 150
Unit
V
V
V
mA
mA
mA
mA
mW
_C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high--impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND
≤
(V
in
or V
out
)
≤
V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
* Absolute maximum continuous ratings are those values beyond which damage to the device
may occur. Exposure to these conditions or conditions beyond those indicated may
adversely affect device reliability. Functional operation under absolute--maximum--rated
conditions is not implied.
†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: -- 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
in
V
out
T
A
t
r
, t
f
DC Supply Voltage
DC Input Voltage
DC Output Voltage
Operating Temperature, All Package Types
Input Rise and Fall Time
(Figure 1)
V
CC
= 3.3V
±0.3V
V
CC
=5.0V
±0.5V
Parameter
Min
2.0
0
0
-- 40
0
0
Max
5.5
5.5
V
CC
+ 85
100
20
Unit
V
V
V
_C
ns/V
DC ELECTRICAL CHARACTERISTICS
Symbol
V
IH
Parameter
Minimum High--Level
Input Voltage
Maximum Low--Level
Input Voltage
Minimum High--Level
Output Voltage
V
in
= V
IH
or V
IL
I
OH
= -- 50μA
V
in
= V
IH
or V
IL
I
OH
= -- 4mA
I
OH
= -- 8mA
V
OL
Maximum Low--Level
Output Voltage
V
in
= V
IH
or V
IL
I
OL
= 50μA
V
in
= V
IH
or V
IL
I
OL
= 4mA
I
OL
= 8mA
Test Conditions
V
CC
V
2.0
3.0 to
5.5
2.0
3.0 to
5.5
2.0
3.0
4.5
3.0
4.5
2.0
3.0
4.5
3.0
4.5
1.9
2.9
4.4
2.58
3.94
0.0
0.0
0.0
0.1
0.1
0.1
0.36
0.36
2.0
3.0
4.5
T
A
= 25°C
Min
1.50
V
CC
x 0.7
0.50
V
CC
x 0.3
1.9
2.9
4.4
2.48
3.80
0.1
0.1
0.1
0.44
0.44
V
Typ
Max
T
A
= - 40 to 85°C
-
Min
1.50
V
CC
x 0.7
0.50
V
CC
x 0.3
Max
Unit
V
V
IL
V
V
OH
V
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3
DC ELECTRICAL CHARACTERISTICS
Symbol
I
in
I
OZ
Parameter
Maximum Input
Leakage Current
Maximum
Three--State Leakage
Current
Maximum Quiescent
Supply Current
Test Conditions
V
in
= 5.5V or GND
V
in
= V
IL
or V
IH
V
out
= V
CC
or GND
V
in
= V
CC
or GND
V
CC
V
0 to 5.5
5.5
T
A
= 25°C
Min
Typ
Max
±
0.1
±
0.25
T
A
= - 40 to 85°C
-
Min
Max
±
1.0
±
2.5
Unit
μA
μA
I
CC
5.5
4.0
40.0
μA
AC ELECTRICAL CHARACTERISTICS
(Input t
r
= t
f
= 3.0ns)
T
A
= 25°C
Symbol
t
PLH
,
t
PHL
Parameter
Maximum Propagation Delay,
A to Y
(Figures 1 and 3)
Test Conditions
V
CC
= 3.3
±
0.3V
V
CC
= 5.0
±
0.5V
V
CC
= 3.3
±
0.3V
R
L
= 1kΩ
V
CC
= 5.0
±
0.5V
R
L
= 1kΩ
V
CC
= 3.3
±
0.3V
R
L
= 1kΩ
V
CC
= 5.0
±
0.5V
R
L
= 1kΩ
V
CC
= 3.3
±
0.3V
(Note 1)
V
CC
= 5.0
±
0.5V
(Note 1)
C
in
C
out
Maximum Input Capacitance
Maximum Three--State Output
Capacitance (Output in High
Impedance State)
C
L
= 15pF
C
L
= 50pF
C
L
= 15pF
C
L
= 50pF
C
L
= 15pF
C
L
= 50pF
C
L
= 15pF
C
L
= 50pF
C
L
= 50pF
C
L
= 50pF
C
L
= 50pF
C
L
= 50pF
4
6
Min
Typ
4.8
7.3
3.7
5.2
6.8
9.3
4.7
6.2
11.2
6.0
Max
7.0
10.5
5.0
7.0
10.5
14.0
7.2
9.2
15.4
8.8
1.5
1.0
10
10
T
A
= - 40 to 85°C
-
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max
8.5
12.0
6.0
8.0
12.5
16.0
8.5
10.5
17.5
10.0
ns
ns
pF
pF
ns
ns
Unit
ns
t
PZL
,
t
PZH
Output Enable TIme,
OEn to Y
(Figures 2 and 4)
t
PLZ
,
t
PHZ
Output Disable Time,
OEn to Y
(Figures 2 and 4)
t
OSLH
,
t
OSHL
Output to Output Skew
Typical @ 25°C, V
CC
= 5.0V
17
C
PD
Power Dissipation Capacitance (Note 2)
pF
1. Parameter guaranteed by design. t
OSLH
= |t
PLHm
-- t
PLHn
|, t
OSHL
= |t
PHLm
-- t
PHLn
|.
2. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
¯
V
CC
¯
f
in
+ I
CC
/8 (per bit). C
PD
is used to determine the no--load
dynamic power consumption; P
D
= C
PD
¯
V
CC2
¯
f
in
+ I
CC
¯
V
CC
.
NOISE CHARACTERISTICS
(Input t
r
= t
f
= 3.0ns, C
L
= 50pF, V
CC
= 5.0V)
T
A
= 25°C
Symbol
V
OLP
V
OLV
V
IHD
V
ILD
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
Parameter
Typ
0.9
-- 0.9
Max
1.2
-- 1.2
3.5
1.5
Unit
V
V
V
V
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4
SWITCHING WAVEFORMS
V
CC
V
CC
A
t
PHL
50% V
CC
Y
50%
t
PLH
GND
Y
50% V
CC
V
OL
+0.3V
Y
t
PZH
50% V
CC
t
PHZ
V
OH
--0.3V
HIGH
IMPEDANCE
OE1 or OE2
50%
t
PZL
t
PLZ
50%
GND
HIGH
IMPEDANCE
Figure 1.
Figure 2.
TEST CIRCUITS
TEST
POINT
OUTPUT
DEVICE
UNDER
TEST
C
L
*
DEVICE
UNDER
TEST
OUTPUT
TEST
POINT
1kΩ
C
L
*
CONNECT TO V
CC
WHEN
TESTING t
PLZ
AND t
PZL
.
CONNECT TO GND WHEN
TESTING t
PHZ
AND t
PZH
.
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 3.
Figure 4.
INPUT EQUIVALENT CIRCUIT
INPUT
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