Am29DL640H
Data Sheet
For new designs, S29JL064H supersedes Am29DL640H and is the factory-recommended migration
path for this device. Please refer to the S29JL064H Datasheet for specifications and ordering
information.
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number
27082
Revision
A
Amendment
6
Issue Date
February 9, 2005
THIS PAGE LEFT INTENTIONALLY BLANK.
For new designs, S29JL064H supersedes Am29DL640H and is the factory-recommended migration path for this
device. Please refer to the S29JL064H Datasheet for specifications and ordering information.
Am29DL640H
64 Megabit (8 M x 8-Bit/4 M x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
■
Simultaneous Read/Write operations
— Data can be continuously read from one bank while
executing erase/program functions in another bank.
— Zero latency between read and write operations
■
Flexible Bank
TM
architecture
— Read may occur in any of the three banks not being
written or erased.
— Four banks may be grouped by customer to achieve
desired bank divisions.
■
Boot Sectors
— Top and bottom boot sectors in the same device
— Any combination of sectors can be erased
■
Manufactured on 0.13 µm process technology
■
Secured Silicon Sector: Extra 256 Byte sector
—
Factory locked and identifiable:
16 bytes available for
secure, random factory Electronic Serial Number;
verifiable as factory locked through autoselect
function. ExpressFlash option allows entire sector to
be available for factory-secured data
—
Customer lockable:
One-time programmable only.
Once locked, data cannot be changed
■
Zero Power Operation
— Sophisticated power management circuits reduce
power consumed during inactive periods to nearly
zero.
■
Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash standard
■
Ultra low power consumption (typical values)
— 2 mA active read current at 1 MHz
— 10 mA active read current at 5 MHz
— 200 nA in standby or automatic sleep mode
■
Minimum 1 million erase cycles guaranteed per
sector
■
20 year data retention at 125°C
— Reliable operation for the life of the system
SOFTWARE FEATURES
■
Data Management Software (DMS)
— AMD-supplied software manages data programming,
enabling EEPROM emulation
■
Supports Common Flash Memory Interface (CFI)
■
Erase Suspend/Erase Resume
— Suspends erase operations to read data from, or
program data to, a sector that is not being erased,
then resumes the erase operation.
■
Data# Polling and Toggle Bits
— Provides a software method of detecting the status of
program or erase cycles
■
Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
HARDWARE FEATURES
■
Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or erase
cycle completion
■
Hardware reset pin (RESET#)
— Hardware method of resetting the internal state
machine to the read mode
■
WP#/ACC input pin
— Write protect (WP#) function protects sectors 0, 1,
140, and 141, regardless of sector protect status
— Acceleration (ACC) function accelerates program
timing
■
Sector protection
— Hardware method to prevent any program or erase
operation within a sector
— Temporary Sector Unprotect allows changing data in
protected sectors in-system
PACKAGE OPTIONS
■
63-ball Fine Pitch BGA
■
48-pin TSOP
PERFORMANCE CHARACTERISTICS
■
High performance
— Access time as fast as 55 ns
— Program time: 4 µs/word typical using accelerated
programming function
Publication#
27082
Rev:
A
Amendment/6
Issue Date:
February 9, 2005
Refer to AMD’s Website (www.amd.com) for the latest information.
GENERAL DESCRIPTION
The Am29DL640H is a 64 megabit, 3.0 volt-only flash
memory device, organized as 4,194,304 words of 16
bits each or 8,388,608 bytes of 8 bits each. Word
mode data appears on DQ15–DQ0; byte mode data
appears on DQ7–DQ0. The device is designed to be
programmed in-system with the standard 3.0 volt V
CC
supply, and can also be programmed in standard
EPROM programmers.
The device is available with an access time of 55, 60,
70, or 90 ns and is offered in 48-pin TSOP and 63-ball
F i n e P i t c h B G A p a ck a g e s . S t a n d a r d c o n t r o l
pins—chip enable (CE#), write enable (WE#), and out-
put enable (OE#)—control normal read and write op-
erations, and avoid bus contention issues.
The device requires only a
single 3.0 volt power sup-
ply
for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
Factory locked parts provide several options. The Se-
cured Silicon Sector may store a secure, random 16
byte ESN (Electronic Serial Number), customer code
(programmed through AMD’s ExpressFlash service),
or both. Customer Lockable parts may utilize the Se-
cured Silicon Sector as bonus space, reading and writ-
ing like any other flash sector, or may permanently
lock their own code there.
DMS (Data Management Software)
allows systems
to easily take advantage of the advanced architecture
of the simultaneous read/write product line by allowing
removal of EEPROM devices. DMS will also allow the
system software to be simplified, as it will perform all
functions necessary to modify data in file structures,
as opposed to single-byte modifications. To write or
update a particular piece of data (a phone number or
configuration data, for example), the user only needs
to state which piece of data is to be updated, and
where the updated data is located in the system. This
i s a n a d va n t a g e c o m p a r e d t o s y s t e m s w h e r e
user-written software must keep track of the old data
location, status, logical to physical translation of the
data onto the Flash memory device (or memory de-
vices), and more. Using DMS, user-written software
does not need to interface with the Flash memory di-
rectly. Instead, the user's software accesses the Flash
memory by calling one of only six functions. AMD pro-
vides this software to simplify system design and soft-
ware integration efforts.
The device offers complete compatibility with the
JEDEC 42.4 single-power-supply Flash command
set standard.
Commands are written to the command
register using standard microprocessor write timings.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
The host system can detect whether a program or
erase operation is complete by using the device
sta-
tus bits:
RY/BY# pin, DQ7 (Data# Polling) and
DQ6/DQ2 (toggle bits). After a program or erase cycle
has been completed, the device automatically returns
to the read mode.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via program-
ming equipment.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby mode.
Power consumption is greatly re-
duced in both modes.
Simultaneous Read/Write Operations with
Zero Latency
The Simultaneous Read/Write architecture provides
simultaneous operation
by dividing the memory
space into
four banks,
two 8 Mb banks with small and
large sectors, and two 24 Mb banks of large sectors.
Sector addresses are fixed, system software can be
used to form user-defined bank groups.
During an Erase/Program operation, any of the three
non-busy banks may be read from. Note that only two
banks can operate simultaneously. The device can im-
prove overall system performance by allowing a host
system to program or erase in one bank, then
immediately and simultaneously read from the other
bank, with zero latency. This releases the system from
waiting for the completion of program or erase
operations.
The Am29DL640H can be organized as both a top and
bottom boot sector configuration.
Bank
Bank 1
Bank 2
Bank 3
Bank 4
Megabits
8 Mb
24 Mb
24 Mb
8 Mb
Sector Sizes
Eight 8 Kbyte/4 Kword,
Fifteen 64 Kbyte/32 Kword
Forty-eight 64 Kbyte/32 Kword
Forty-eight 64 Kbyte/32 Kword
Eight 8 Kbyte/4 Kword,
Fifteen 64 Kbyte/32 Kword
Am29DL640H Features
The
Secured Silicon Sector
is an extra 256 byte sec-
tor capable of being permanently locked by AMD or
customers. The Secured Silicon Customer Indicator
Bit (DQ6) is permanently set to 1 if the part has been
customer locked, permanently set to 0 if the part has
been factory locked, and is 0 if customer lockable. This
way, customer lockable parts can never be used to re-
place a factory locked part.
2
Am29DL640H
February 9, 2005
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . .
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .
Device Bus Operations . . . . . . . . . . . . . . . . . . . . .
4
4
5
6
7
8
DQ6: Toggle Bit I .................................................................... 29
Figure 7. Toggle Bit Algorithm........................................................ 29
DQ2: Toggle Bit II ................................................................... 30
Reading Toggle Bits DQ6/DQ2 ............................................... 30
DQ5: Exceeded Timing Limits ................................................ 30
DQ3: Sector Erase Timer ....................................................... 30
Table 13. Write Operation Status ................................................... 31
Table 1. Am29DL640H Device Bus Operations ................................8
Requirements for Reading Array Data ..................................... 8
Writing Commands/Command Sequences .............................. 9
Accelerated Program Operation ............................................... 9
Autoselect Functions ................................................................ 9
Simultaneous Read/Write Operations with Zero Latency ......... 9
Automatic Sleep Mode ........................................................... 10
RESET#: Hardware Reset Pin ............................................... 10
Output Disable Mode .............................................................. 10
Table 2. Am29DL640H Sector Architecture ....................................10
Table 3. Bank Address ....................................................................13
Table 5. Am29DL640H Autoselect Codes, (High Voltage Method) 14
Table 6. Am29DL640H Boot Sector/Sector Block Addresses for
Protection/Unprotection ...................................................................15
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 32
Figure 8. Maximum Negative Overshoot Waveform ...................... 32
Figure 9. Maximum Positive Overshoot Waveform........................ 32
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 10. I
CC1
Current vs. Time (Showing Active and
Automatic Sleep Currents) ............................................................. 34
Figure 11. Typical I
CC1
vs. Frequency ............................................ 34
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 12. Test Setup.................................................................... 35
Figure 13. Input Waveforms and Measurement Levels ................. 35
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 36
Read-Only Operations ........................................................... 36
Figure 14. Read Operation Timings ............................................... 36
Write Protect (WP#) ................................................................ 15
Table 7. WP#/ACC Modes ..............................................................16
Hardware Reset (RESET#) .................................................... 37
Figure 15. Reset Timings ............................................................... 37
Temporary Sector Unprotect .................................................. 16
Figure 1. Temporary Sector Unprotect Operation........................... 16
Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 17
Word/Byte Configuration (BYTE#) .......................................... 38
Figure 16. BYTE# Timings for Read Operations............................ 38
Figure 17. BYTE# Timings for Write Operations............................ 38
Secured Silicon Sector
Flash Memory Region ............................................................ 18
Figure 3. Secured Silicon Sector Protect Verify .............................. 19
Erase and Program Operations .............................................. 39
Figure 18. Program Operation Timings..........................................
Figure 19. Accelerated Program Timing Diagram..........................
Figure 20. Chip/Sector Erase Operation Timings ..........................
Figure 21. Back-to-back Read/Write Cycle Timings ......................
Figure 22. Data# Polling Timings (During Embedded Algorithms).
Figure 23. Toggle Bit Timings (During Embedded Algorithms)......
Figure 24. DQ2 vs. DQ6.................................................................
40
40
41
42
42
43
43
Hardware Data Protection ...................................................... 19
Low VCC Write Inhibit ............................................................ 19
Write Pulse “Glitch” Protection ............................................... 19
Logical Inhibit .......................................................................... 19
Power-Up Write Inhibit ............................................................ 19
Common Flash Memory Interface (CFI) . . . . . . . 19
Command Definitions . . . . . . . . . . . . . . . . . . . . . 23
Reading Array Data ................................................................ 23
Reset Command ..................................................................... 23
Autoselect Command Sequence ............................................ 23
Enter Secured Silicon Sector/Exit Secured Silicon Sector
Command Sequence .............................................................. 23
Byte/Word Program Command Sequence ............................. 24
Unlock Bypass Command Sequence ..................................... 24
Figure 4. Program Operation .......................................................... 25
Temporary Sector Unprotect .................................................. 44
Figure 25. Temporary Sector Unprotect Timing Diagram .............. 44
Figure 26. Sector/Sector Block Protect and
Unprotect Timing Diagram ............................................................. 45
Alternate CE# Controlled Erase and Program Operations ..... 46
Figure 27. Alternate CE# Controlled Write (Erase/Program)
Operation Timings.......................................................................... 47
Chip Erase Command Sequence ........................................... 25
Sector Erase Command Sequence ........................................ 25
Figure 5. Erase Operation............................................................... 26
Erase Suspend/Erase Resume Commands ........................... 26
Write Operation Status . . . . . . . . . . . . . . . . . . . . 28
DQ7: Data# Polling ................................................................. 28
Figure 6. Data# Polling Algorithm ................................................... 28
Erase And Programming Performance. . . . . . . . 48
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 48
TSOP & BGA Pin Capacitance. . . . . . . . . . . . . . . 48
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
FBE063—63-Ball Fine-Pitch Ball Grid Array (fBGA)
12 x 11 mm package .............................................................. 49
TS 048—48-Pin Standard TSOP ............................................ 50
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 51
TS 048—48-Pin Standard TSOP. . . . . . . . . . . . . . 52
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 53
February 9, 2005
Am29DL640H
3
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