Synchronous Output Enable. When LOW, Q outputs will go LOW and Qb
outputs will go HIGH on the next negative transition of IN input. The internal
DFF register is clocked on the falling edge of IN input; see Figure 23. The EN
pin has an internal pullup resistor and defaults HIGH when left open.
Inverted Differential Input
The V
REF_AC
reference output can be used to rebias capacitor−coupled
differential or single−ended input signals. For the capacitor−coupled IN and/or
INb inputs, V
REF_AC
should be connected to the VT pin and bypassed to
ground with a 0.01
mF
capacitor.
Internal 100
W
Center−tapped Termination Pin for IN and IN
Non−inverted Differential Input. (Note 2)
Negative Supply Voltage.
Positive Supply Voltage.
Non−inverted IN output. Typically loaded with 100
W
receiver termination
resistor across differential pair.
Inverted IN output. Typically loaded with 100
W
receiver termination resistor
across differential pair.
The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected
to the die for improved heat transfer out of package. The exposed pad must be
attached to a heat−sinking conduit. The pad is not electrically connected to the
die, but is recommended to be electrically and thermally connected to GND on
the PC board.
9
10
IN
V
REF_AC
LVPECL, CML, LVDS
LVPECL Output
11
12
13
14
15
16
−
V
T
IN
GND
V
CC
Q0
Q0
EP
LVPECL Output
LVPECL, CML, LVDS
−
−
LVDS Output
LVDS Output
−
2. In the differential configuration, when the input termination pin (VT) is connected to a termination voltage or left open, and if no signal is applied
on IN/IN inputs, then the device will be susceptible to self−oscillation.
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2
NB6N14S
Table 3. ATTRIBUTES
Characteristics
Moisture Sensitivity (Note 3)
Flammability Rating
ESD Protection
EN Input Pullup Resistor
−
R
PU
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
Oxygen Index: 28 to 34
Human Body Model
Machine Model
Value
Level 1
UL 94 V−0 @ 0.125 in
> 2 kV
> 200 V
37 kW
225
Table 4. MAXIMUM RATINGS
Symbol
V
CC
V
IN
I
IN
I
OSC
Parameter
Positive Power Supply
Positive Input
Input Current Through R
T
(50
W
Resistor)
Output Short Circuit Current
Line−to−Line (Q to Q)
Line−to−End (Q or Q to GND)
TIA/EIA
−
644 Compliant
V
REF_AC
Sink/Source Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient) (Note 4)
Thermal Resistance (Junction−to−Case)
Wave Solder
Pb−Free
0 lfpm
500 lfpm
1S2P (Note 4)
QFN−16
QFN−16
QFN−16
QFN−16
Condition 1
GND = 0 V
GND = 0 V
Static
Surge
Q or Q
Q to Q to GND
Continuous
Continuous
V
IN
≤
V
CC
Condition 2
Rating
3.8
3.8
35
70
12
24
"0.5
−40
to +85
−65
to +150
41.6
35.2
4.0
265
Unit
V
V
mA
mA
mA
I
REF_AC
T
A
T
stg
q
JA
q
JC
T
sol
mA
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
4. JEDEC standard multilayer board
−
1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad.
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3
NB6N14S
Table 5. DC CHARACTERISTICS
V
CC
= 3.0 V to 3.6 V, GND = 0 V, T
A
=
−40°C
to +85°C
Symbol
I
CC
V
th
V
IH
V
IL
V
REF_AC
V
IHD
V
ILD
V
CMR
V
ID
R
TIN
V
OD
DV
OD
V
OS
DV
OS
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
Characteristic
Power Supply Current (Note 9)
Min
Typ
65
Max
100
Unit
mA
DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED
(Figures 14, 15, 19, and 21)
Input Threshold Reference Voltage Range (Note 8)
Single−ended Input HIGH Voltage
Single−ended Input LOW Voltage
Reference Output Voltage (Note 11)
GND +100
V
th
+ 100
GND
V
CC
−
1.600
100
GND
GND + 50
100
40
50
V
CC
−
1.425
V
CC
−
100
V
CC
V
th
−
100
V
CC
−
1.300
V
CC
V
CC
−
100
V
CC
−
50
V
CC
60
mV
mV
mV
V
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY
(Figures 10, 11, 12, 13, 20, and 22)
Differential Input HIGH Voltage
Differential Input LOW Voltage
Input Common Mode Range (Differential Configuration)
Differential Input Voltage (V
IHD
−
V
ILD
)
Internal Input Termination Resistor
mV
mV
mV
mV
W
LVDS OUTPUTS
(Note 5)
Differential Output Voltage
Change in Magnitude of V
OD
for Complementary Output States
(Note 10)
Offset Voltage (Figure 18)
Change in Magnitude of V
OS
for Complementary Output States
(Note 10)
Output HIGH Voltage (Note 6)
Output LOW Voltage (Note 7)
900
250
0
1125
0
1
1425
1075
1
450
25
1375
25
1600
mV
mV
mV
mV
mV
mV
LVTTL/LVCMOS INPUTS
Input HIGH Voltage (Note 7, 8)
Input LOW Voltage (Note 7, 8)
Input HIGH Current
Input LOW Current
2.0
GND
−150
−150
V
CC
0.8
150
150
V
V
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. LVDS outputs require 100
W
receiver termination resistor between differential pair. See Figure 17.
6. V
OH
max = V
OS
max +
½
V
OD
max.
7. V
OL
max = V
OS
min
−
½
V
OD
max.
8. V
th
is applied to the complementary input when operating in single−ended mode.
9. Input termination pins open, D/D at the DC level within V
CMR
and output pins loaded with R
L
= 100
W
across differential.
10. Parameter guaranteed by design verification not tested in production.
11. V
REF_AC
used to rebias capacitor−coupled inputs only (see Figures 14 and 15).
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4
NB6N14S
Table 6. AC CHARACTERISTICS
V
CC
= 3.0 V to 3.6 V, GND = 0 V; (Note 12)
−40°C
Symbol
f
inMax
V
OUTPP
Characteristic
Maximum Input Clock Frequency
Output Voltage Amplitude (@ V
INPPmin
)
(Figure 4)
Maximum Operating Data Rate
Differential Input to Differential Output
Propagation Delay
Setup Time
Hold Time
Within Device Skew (Note 17)
Device−to−Device Skew (Note 16)
RMS Random Clock Jitter (Note 14)
Deterministic Jitter (Note 15)
f
in
= 1.0 GHz
f
in
= 1.5 GHz
f
DATA
= 622 Mb/s
f
DATA
= 1.5 Gb/s
f
DATA
= 2.488 Gb/s
100
Q, Q
60
120
f
in
≤
1.0 GHz
f
in
= 1.5 GHz
f
in
= 2.0 GHz
Min
2.0
220
200
170
1.5
300
300
500
350
300
270
2.5
450
60
70
5
30
0.5
0.5
6.0
7.0
10
20
200
1.0
1.0
20
20
20
V
CC
−
GND
190
100
60
120
600
Typ
Max
Min
2.0
220
200
170
1.5
300
300
500
350
300
270
2.5
450
60
70
5
30
0.5
0.5
6.0
7.0
10
20
200
1.0
1.0
20
20
20
V
CC
−
GND
190
100
60
120
600
25°C
Typ
Max
Min
2.0
220
200
170
1.5
300
300
500
350
300
270
2.5
450
60
70
5
30
0.5
0.5
6.0
7.0
10
20
200
1.0
1.0
20
20
20
V
CC
−
GND
190
ps
ps
600
85°C
Typ
Max
Unit
GHz
mV
f
DATA
t
PLH
,
t
PHL
t
s
t
h
t
SKEW
t
JITTER
Gb/s
ps
V
INPP
t
r
t
f
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 13)
Output Rise/Fall Times @ 250 MHz
(20%
−
80%)
mV
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
12. Measured by forcing V
INPPmin
with 50% duty cycle clock source and V
CC
−
1400 mV offset. All loading with an external R
L
= 100
W.
Input
edge rates 150 ps (20%−80%). See Figure 17.
13. Input voltage swing is a single−ended measurement operating in differential mode.
14. RMS jitter with 50% Duty Cycle clock signal at 750 MHz.
15. Deterministic jitter with input NRZ data at PRBS 2
23
−1
and K28.5.
16. Skew is measured between outputs under identical transition @ 250 MHz.
17. The worst case condition between Q0/Q0 and Q1/Q1 from either D0/D0 or D1/D1, when both outputs have the same transition.
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