Features
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Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
Data Sheet Describes Mode 0 Operation
Low-voltage and Standard-voltage Operation
– 2.7 (V
CC
= 2.7V to 5.5V)
– 1.8 (V
CC
= 1.8V to 5.5V)
20 MHz Clock Rate (5V)
64-byte Page Mode and Byte Write Operation
Block Write Protection
– Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for
Both Hardware and Software Data Protection
Self-timed Write Cycle (5 ms Max)
High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: >100 Years
Automotive Grade, Extended Temperature and Lead-free/Halogen-free
Devices Available
8-lead PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-ball dBGA2 and
8-lead SAP Packages
Die Sales: Wafer Form, Waffle Pack, and Bumped Die
SPI Serial
EEPROMs
128K (16,384 x 8)
256K (32,768 x 8)
Description
The AT25128A/256A provides 131,072/262,144 bits of serial electrically-erasable
programmable read only memory (EEPROM) organized
as
16,384/32,768 words of
8
bits each. The device is optimized for use in many industrial
and
commercial
appli-
cations where low-power
and
low-voltage operation
are
essential. The devices
are
available
in space saving
8-lead
PDIP,
8-lead
EIAJ
SOIC, 8-lead
JEDEC
SOIC, 8-
lead TSSOP,
8-ball
dBGA2
and 8-lead SAP
packages. In
addition,
the entire family is
available
in 2.7V (2.7V to 5.5V)
and
1.8V (1.8V to 5.5V) versions.
The AT25128A/256A is enabled through the Chip
Select
pin (CS)
and accessed
via
a 3-wire
interface consisting of
Serial
Data Input (SI),
Serial
Data Output (SO),
and
Serial
Clock (SCK). All programming cycles
are
completely self-timed,
and
no sepa-
rate Erase cycle is required before Write.
8-lead PDIP
8-lead SOIC
VCC
HOLD
SCK
SI
CS
SO
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
AT25128A
AT25256A
Table 1.
Pin Configurations
Pin Name
CS
SCK
SI
SO
GND
VCC
WP
HOLD
NC
Function
Chip
Select
Serial
Data Clock
Serial
Data Input
Serial
Data Output
Ground
Power
Supply
Write Protect
Suspends Serial
Input
No Connect
CS
SO
WP
GND
1
2
3
4
8
7
6
5
8-lead TSSOP
CS
SO
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
VCC
HOLD
SCK
SI
8-lead SAP
8
7
6
5
1
2
3
4
CS
SO
WP
GND
8-ball dBGA2
VCC
HOLD
SCK
SI
8
7
6
5
1
2
3
4
Bottom View
CS
SO
WP
GND
Bottom View
3368H–SEEPR–8/05
1
Block Write protection is enabled by programming the status register with top ¼, top ½
or entire
array
of write protection.
Separate
Program Enable
and
Program Disable
instructions
are
provided for
additional
data protection. Hardware data protection is pro-
vided via the WP pin to protect
against
inadvertent write
attempts
to the status register.
The HOLD pin may be used to suspend
any
serial communication without resetting the
serial sequence.
Absolute Maximum Ratings*
Operating Temperature......................................−55°C to +125°C
Storage
Temperature
.........................................−65°C
to +150°C
Voltage on Any Pin
with Respect to Ground
........................................ −1.0V
to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
*NOTICE:
Stresses
beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is
a
stress rating only
and
functional
operation of the device
at
these or
any
other condi-
tions beyond those indicated in the operational sec-
tions of this specification is not implied. Exposure to
absolute
maximum rating conditions for extended
periods may
affect
device reliability.
Figure 1.
Block Diagram
16384/32768 x 8
Table 2.
Pin Capacitance
(1)
Applicable over recommended operating range from T
A
= 25°C, f = 1.0 MHz, V
CC
= +5.0V (unless otherwise noted)
Symbol
C
OUT
C
IN
Note:
Test Conditions
Output Capacitance (SO)
Input Capacitance (CS,
SCK, SI,
WP, HOLD)
1. This parameter is characterized
and
is not 100% tested.
Max
8
6
Units
pF
pF
Conditions
V
OUT
= 0V
V
IN
= 0V
2
AT25128A/256A
3368H–SEEPR–8/05
AT25128A/256A
Table 3.
DC Characteristics
Applicable over recommended operating range from T
AI
=
−
40°C to +85°C, V
CC
= +1.8V to +5.5V,
T
AE
=
−
40°C to +125°C, V
CC
= +1.8V to +5.5V(unless otherwise noted)
Symbol
V
CC1
V
CC2
V
CC3
I
CC1
I
CC2
I
CC3
I
SB1
I
SB2
I
SB3
I
IL
I
OL
V
IL(1)
V
IH(1)
V
OL1
V
OH1
V
OL2
V
OH2
Note:
Parameter
Supply
Voltage
Supply
Voltage
Supply
Voltage
Supply
Current
Supply
Current
Supply
Current
Standby
Current
Standby
Current
Standby
Current
Input Leakage
Output Leakage
Input Low-voltage
Input High-voltage
Output Low-voltage
Output High-voltage
Output Low-voltage
Output High-voltage
3.6
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
≤
3.6V
I
OL
=
3.0
mA
I
OH
=
−1.6
mA
I
OL
= 0.15 mA
I
OH
=
−100
µA
V
CC
−0.2
V
CC
−0.8
0.2
V
CC
= 5.0V
at
20 MHz,
SO
= Open,
Read
V
CC
= 5.0V
at
10 MHz,
SO
= Open, Read, Write
V
CC
= 5.0V
at
1 MHz,
SO
= Open, Read, Write
V
CC
= 1.8V, CS = V
CC
V
CC
= 2.7V, CS = V
CC
V
CC
= 5.0V, CS = V
CC
V
IN
= 0V to V
CC
V
IN
= 0V to V
CC
, T
AC
= 0°C to 70°C
−3.0
−3.0
−1.0
V
CC
x 0.7
Test Condition
Min
1.8
2.7
4.5
9.0
5.0
2.2
0.2
0.5
2.0
Typ
Max
5.5
5.5
5.5
10.0
7.0
3.5
3.0
3.0
5.0
3.0
3.0
V
CC
x 0.3
V
CC
+ 0.5
0.4
Units
V
V
V
mA
mA
mA
µA
µA
µA
µA
µA
V
V
V
V
V
V
1. V
IL
and
V
IH
max
are
reference only
and are
not tested.
Table 4.
AC Characteristics
Applicable over recommended operating range from T
AI
=
−
40°C to +
85°C,
T
AE
=
−
40°C to +125°C, V
CC
= As
Specified,
CL = 1 TTL Gate
and 30
pF (unless otherwise noted)
Symbol
f
SCK
Parameter
SCK
Clock Frequency
Voltage
4.5−5.5
2.7−5.5
1.8−5.5
4.5−5.5
2.7−5.5
1.8−5.5
4.5−5.5
2.7−5.5
1.8−5.5
4.5−5.5
2.7−5.5
1.8−5.5
20
40
80
Min
0
0
0
Max
20
10
5
2
2
2
2
2
2
Units
MHz
t
RI
Input Rise Time
µs
t
FI
Input Fall Time
µs
t
WH
SCK
High Time
ns
3
3368H–SEEPR–8/05
Table 4.
AC Characteristics (Continued)
Applicable over recommended operating range from T
AI
=
−
40°C to +
85°C,
T
AE
=
−
40°C to +125°C, V
CC
= As
Specified,
CL = 1 TTL Gate
and 30
pF (unless otherwise noted)
Symbol
t
WL
Parameter
SCK
Low Time
Voltage
4.5−5.5
2.7−5.5
1.8−5.5
4.5−5.5
2.7−5.5
1.8−5.5
4.5−5.5
2.7−5.5
1.8−5.5
4.5−5.5
2.7−5.5
1.8−5.5
4.5−5.5
2.7−5.5
1.8−5.5
4.5−5.5
2.7−5.5
1.8−5.5
4.5−5.5
2.7−5.5
1.8−5.5
4.5−5.5
2.7−5.5
1.8−5.5
4.5−5.5
2.7−5.5
1.8−5.5
4.5−5.5
2.7−5.5
1.8−5.5
4.5−5.5
2.7−5.5
1.8−5.5
4.5−5.5
2.7−5.5
1.8−5.5
4.5−5.5
2.7−5.5
1.8−5.5
4.5−5.5
2.7−5.5
1.8−5.5
1M
Min
20
40
80
100
100
200
100
100
200
100
100
200
5
10
20
5
10
20
5
10
20
5
10
20
0
0
0
0
0
0
0
0
0
25
50
100
25
50
100
25
50
100
5
5
5
20
40
80
Max
Units
ns
t
CS
CS High Time
ns
t
CSS
CS
Setup
Time
ns
t
CSH
CS Hold Time
ns
t
SU
Data In
Setup
Time
ns
t
H
Data In Hold Time
ns
t
HD
Hold
Setup
Time
ns
t
CD
Hold Hold Time
ns
t
V
Output Valid
ns
t
HO
Output Hold Time
ns
t
LZ
Hold to Output Low Z
ns
t
HZ
Hold to Output High Z
ns
t
DIS
Output Disable Time
ns
t
WC
Endurance
(1)
Note:
Write Cycle Time
5.0V, 25°C, Page Mode
ms
Write Cycles
1. This parameter is characterized
and
is not 100% tested. Contact Atmel for further information.
4
AT25128A/256A
3368H–SEEPR–8/05
AT25128A/256A
Serial Interface
Description
MASTER:
The device that generates the serial clock.
SLAVE:
Because the serial clock pin (SCK) is
always an
input, the AT25128A/256A
always
operates
as a
slave.
TRANSMITTER/RECEIVER:
The AT25128A/256A has separate pins designated for
data transmission (SO)
and
reception (SI).
MSB:
The Most
Significant
Bit (MSB) is the first bit transmitted
and
received.
SERIAL OP-CODE:
After the device is selected with CS going low, the first byte will
be received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE:
If
an
invalid op-code is received, no data will be shifted into the
AT25128A/256A,
and
the serial output pin (SO) will remain in
a
high impedance state
until the falling edge of CS is detected
again.
This will reinitialize the serial
communication.
CHIP SELECT:
The AT25128A/256A is selected when the CS pin is low. When the
device is not selected, data will not be
accepted
via the
SI
pin,
and
the serial output pin
(SO) will remain in
a
high impedance state.
HOLD:
The HOLD pin is used in conjunction with the CS pin to select the
AT25128A/256A. When the device is selected
and a
serial sequence is underway,
HOLD can be used to pause the serial communication with the master device without
resetting the serial sequence. To pause, the HOLD pin must be brought low while the
SCK
pin is low. To resume serial communication, the HOLD pin is brought high while the
SCK
pin is low (SCK may still toggle during HOLD). Inputs to the
SI
pin will be ignored
while the
SO
pin is in the high impedance state.
WRITE PROTECT:
The write protect pin (WP) will
allow
normal read/write operations
when held high. When the WP pin is brought low
and
WPEN bit is “1”,
all
write opera-
tions to the status register
are
inhibited. WP going low while CS is still low will interrupt
a
write to the status register. If the internal write cycle has
already
been initiated, WP
going low will have no effect on
any
write operation to the status register. The WP pin
function is blocked when the WPEN bit in the status register is “0”. This will
allow
the
user to install the AT25128A/256A in
a
system with the WP pin tied to ground
and
still be
able
to write to the status register. All WP pin functions
are
enabled when the WPEN bit
is set to “1”.
5
3368H–SEEPR–8/05
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