DEMO KIT AVAILABLE
DS26519
16-Port T1/E1/J1 Transceiver
www.maxim-ic.com
GENERAL DESCRIPTION
The DS26519 is a single-chip 16-port framer and line
interface unit (LIU) combination for T1, E1, and J1
applications. Each port is independently configurable,
supporting both long-haul and short-haul lines. The
DS26519 is nearly software compatible with the
DS26528 and its derivatives.
FEATURES
16 Complete T1, E1, or J1 Long-Haul/
Short-Haul Transceivers (LIU Plus Framer)
Independent T1, E1, or J1 Selections for Each
Transceiver
Software-Selectable Transmit- and Receive-
Side Termination for 100Ω T1 Twisted Pair,
110Ω J1 Twisted Pair, 120Ω E1 Twisted Pair,
and 75Ω E1 Coaxial Applications
Hitless Protection Switching
Crystal-Less Jitter Attenuators Can Be
Selected for Transmit or Receive Path; Jitter
Attenuator Meets ETS CTR 12/13, ITU-T
G.736, G.742, G.823, and AT&T Pub 62411
External Master Clock Can Be Multiple of
2.048MHz or 1.544MHz for T1/J1 or E1
Operation; This Clock is Internally Adapted
for T1 or E1 Usage in the Host Mode
Receive-Signal Level Indication from -2.5dB
to -36dB in T1 Mode and -2.5dB to -44dB in E1
Mode in Approximate 2.5dB Increments
APPLICATIONS
Routers
Channel Service Units (CSUs)
Data Service Units (DSUs)
Muxes
Switches
Channel Banks
T1/E1 Test Equipment
FUNCTIONAL DIAGRAM
DS26519
T1/E1/J1
NETWORK
T1/J1/E1
Transceiver
x16
BACKPLANE
Transmit Open- and Short-Circuit Detection
LIU LOS in Accordance with G.775, ETS 300
233, and T1.231
Transmit Synchronizer
Flexible Signaling Extraction and Insertion
Using Either the System Interface or
Microprocessor Port
Alarm Detection and Insertion
T1 Framing Formats of D4, SLC-96, and ESF
J1 Support
E1 G.704 and CRC-4 Multiframe
T1-to-E1 Conversion
Features continued in Section
2.
TDM
ORDERING INFORMATION
PART
DS26519G
DS26519G+
DS26519GN
DS26519GN+
TEMP RANGE
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
484 HSBGA
484 HSBGA
484 HSBGA
484 HSBGA
+ Denotes a lead-free/RoHS compliant device.
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
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REV: 120407
DS26519 16-Port T1/E1/J1 Transceiver
TABLE OF CONTENTS
1.
2.
DETAILED DESCRIPTION.................................................................................................9
FEATURE HIGHLIGHTS ..................................................................................................10
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
G
ENERAL
......................................................................................................................................10
L
INE
I
NTERFACE
............................................................................................................................10
C
LOCK
S
YNTHESIZERS
..................................................................................................................10
J
ITTER
A
TTENUATOR
.....................................................................................................................10
F
RAMER
/F
ORMATTER
....................................................................................................................11
S
YSTEM
I
NTERFACE
......................................................................................................................11
HDLC C
ONTROLLERS
...................................................................................................................12
T
EST AND
D
IAGNOSTICS
................................................................................................................12
M
ICROCONTROLLER
P
ARALLEL
P
ORT
.............................................................................................12
S
LAVE
S
ERIAL
P
ERIPHERAL
I
NTERFACE
(SPI) F
EATURES
............................................................12
3.
4.
5.
6.
7.
8.
8.1
APPLICATIONS ...............................................................................................................13
SPECIFICATIONS COMPLIANCE ...................................................................................14
ACRONYMS AND GLOSSARY .......................................................................................16
MAJOR OPERATING MODES.........................................................................................17
BLOCK DIAGRAMS.........................................................................................................18
PIN DESCRIPTIONS ........................................................................................................20
P
IN
F
UNCTIONAL
D
ESCRIPTION
......................................................................................................20
9.
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
FUNCTIONAL DESCRIPTION .........................................................................................33
P
ROCESSOR
I
NTERFACE
................................................................................................................33
SPI Serial Port Mode............................................................................................................................ 33
SPI Functional Timing Diagrams ......................................................................................................... 33
Backplane Clock Generation ............................................................................................................... 35
CLKO Output Clock Generation........................................................................................................... 37
9.1.1
9.1.2
9.2.1
9.2.2
C
LOCK
S
TRUCTURE
.......................................................................................................................35
R
ESETS AND
P
OWER
-D
OWN
M
ODES
..............................................................................................38
I
NITIALIZATION AND
C
ONFIGURATION
..............................................................................................39
Example Device Initialization and Sequence ....................................................................................... 39
General-Purpose I/O Pins .................................................................................................................... 40
9.4.1
9.5.1
G
LOBAL
R
ESOURCES
....................................................................................................................40
P
ER
-P
ORT
R
ESOURCES
................................................................................................................40
D
EVICE
I
NTERRUPTS
.....................................................................................................................41
S
YSTEM
B
ACKPLANE
I
NTERFACE
...................................................................................................43
Elastic Stores ....................................................................................................................................... 43
IBO Multiplexing ................................................................................................................................... 46
H.100 (CT Bus) Compatibility .............................................................................................................. 55
Transmit and Receive Channel Blocking Registers............................................................................. 57
Transmit Fractional Support (Gapped Clock Mode) ............................................................................ 57
Receive Fractional Support (Gapped Clock Mode) ............................................................................. 57
T1 Framing........................................................................................................................................... 58
E1 Framing........................................................................................................................................... 61
T1 Transmit Synchronizer .................................................................................................................... 63
Signaling .............................................................................................................................................. 64
T1 Data Link......................................................................................................................................... 69
E1 Data Link......................................................................................................................................... 71
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9.8.1
9.8.2
9.8.3
9.8.4
9.8.5
9.8.6
9.9
F
RAMERS
......................................................................................................................................58
9.9.1
9.9.2
9.9.3
9.9.4
9.9.5
9.9.6
DS26519 16-Port T1/E1/J1 Transceiver
9.9.7
9.9.8
9.9.9
9.9.10
9.9.11
9.9.12
9.9.13
9.9.14
9.9.15
9.9.16
9.9.17
Maintenance and Alarms ..................................................................................................................... 72
Alarms .................................................................................................................................................. 75
Error Count Registers .......................................................................................................................... 77
DS0 Monitoring Function...................................................................................................................... 79
Transmit Per-Channel Idle Code Generation ...................................................................................... 80
Receive Per-Channel Idle Code Insertion............................................................................................ 80
Per-Channel Loopback ........................................................................................................................ 80
E1 G.706 Intermediate CRC-4 Updating (E1 Mode Only) ................................................................... 80
T1 Programmable In-Band Loop Code Generator............................................................................... 81
T1 Programmable In-Band Loop Code Detection................................................................................ 82
Framer Payload Loopbacks ................................................................................................................. 83
9.10
9.10.1
9.10.2
HDLC C
ONTROLLERS
................................................................................................................84
Receive HDLC Controller..................................................................................................................... 84
Transmit HDLC Controller.................................................................................................................... 87
9.11
9.12
9.12.1
9.12.2
9.12.3
9.12.4
9.12.5
9.12.6
P
OWER
-S
UPPLY
D
ECOUPLING
....................................................................................................89
L
INE
I
NTERFACE
U
NITS
(LIU
S
)....................................................................................................90
LIU Operation....................................................................................................................................... 92
Transmitter ........................................................................................................................................... 93
Receiver ............................................................................................................................................... 97
Hitless Protection Switching (HPS).................................................................................................... 101
Jitter Attenuator.................................................................................................................................. 102
LIU Loopbacks ................................................................................................................................... 103
9.13
9.13.1
9.13.2
B
IT
E
RROR
-R
ATE
T
EST
F
UNCTION
(BERT) ...............................................................................106
BERT Repetitive Pattern Set ............................................................................................................. 107
BERT Error Counter........................................................................................................................... 107
10.
DEVICE REGISTERS .....................................................................................................108
R
EGISTER
L
ISTINGS
.................................................................................................................108
Global Register List............................................................................................................................ 109
Framer Register List........................................................................................................................... 110
LIU and BERT Register List............................................................................................................... 117
10.1.1
10.1.2
10.1.3
10.1
10.2
10.2.1
10.2.2
10.2.3
10.2.4
R
EGISTER
B
IT
M
APS
................................................................................................................118
Global Register Bit Map ..................................................................................................................... 118
Framer Register Bit Map .................................................................................................................... 119
LIU Register Bit Map .......................................................................................................................... 128
BERT Register Bit Map ...................................................................................................................... 129
10.3
10.4
10.4.1
10.4.2
G
LOBAL
R
EGISTER
D
EFINITIONS
...............................................................................................130
F
RAMER
R
EGISTER
D
ESCRIPTIONS
...........................................................................................156
Receive Register Descriptions........................................................................................................... 156
Transmit Register Descriptions.......................................................................................................... 214
10.5
10.6
LIU R
EGISTER
D
EFINITIONS
.....................................................................................................250
BERT R
EGISTER
D
EFINITIONS
.................................................................................................260
T1 R
ECEIVER
F
UNCTIONAL
T
IMING
D
IAGRAMS
..........................................................................268
T1 T
RANSMITTER
F
UNCTIONAL
T
IMING
D
IAGRAMS
....................................................................273
E1 R
ECEIVER
F
UNCTIONAL
T
IMING
D
IAGRAMS
..........................................................................278
E1 T
RANSMITTER
F
UNCTIONAL
T
IMING
D
IAGRAMS
....................................................................282
T
HERMAL
C
HARACTERISTICS
....................................................................................................288
L
INE
I
NTERFACE
C
HARACTERISTICS
..........................................................................................288
11.
FUNCTIONAL TIMING ...................................................................................................268
11.1
11.2
11.3
11.4
12.
OPERATING PARAMETERS.........................................................................................287
12.1
12.2
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DS26519 16-Port T1/E1/J1 Transceiver
13.
AC TIMING CHARACTERISTICS ..................................................................................289
M
ICROPROCESSOR
B
US
AC C
HARACTERISTICS
........................................................................289
SPI Bus Mode .................................................................................................................................... 289
13.1.1
13.1
13.2
13.3
JTAG I
NTERFACE
T
IMING
.........................................................................................................300
S
YSTEM
C
LOCK
AC C
HARACTERISTICS
....................................................................................301
TAP C
ONTROLLER
S
TATE
M
ACHINE
.........................................................................................303
Test-Logic-Reset................................................................................................................................ 303
Run-Test-Idle ..................................................................................................................................... 303
Select-DR-Scan ................................................................................................................................. 303
Capture-DR ........................................................................................................................................ 303
Shift-DR.............................................................................................................................................. 303
Exit1-DR............................................................................................................................................. 303
Pause-DR........................................................................................................................................... 303
Exit2-DR............................................................................................................................................. 303
Update-DR ......................................................................................................................................... 303
Select-IR-Scan ............................................................................................................................... 303
Capture-IR ...................................................................................................................................... 304
Shift-IR............................................................................................................................................ 304
Exit1-IR........................................................................................................................................... 304
Pause-IR......................................................................................................................................... 304
Exit2-IR........................................................................................................................................... 304
Update-IR ....................................................................................................................................... 304
SAMPLE:PRELOAD .......................................................................................................................... 306
BYPASS ............................................................................................................................................. 306
EXTEST ............................................................................................................................................. 306
CLAMP............................................................................................................................................... 306
HIGHZ ................................................................................................................................................ 306
IDCODE ............................................................................................................................................. 306
14.
JTAG BOUNDARY SCAN AND TEST ACCESS PORT ................................................302
14.1.1
14.1.2
14.1.3
14.1.4
14.1.5
14.1.6
14.1.7
14.1.8
14.1.9
14.1.10
14.1.11
14.1.12
14.1.13
14.1.14
14.1.15
14.1.16
14.1
14.2
14.2.1
14.2.2
14.2.3
14.2.4
14.2.5
14.2.6
I
NSTRUCTION
R
EGISTER
...........................................................................................................306
14.3
14.4
14.4.1
14.4.2
14.4.3
JTAG ID C
ODES
......................................................................................................................307
T
EST
R
EGISTERS
.....................................................................................................................307
Boundary Scan Register .................................................................................................................... 307
Bypass Register ................................................................................................................................. 307
Identification Register......................................................................................................................... 307
15.
16.
17.
PIN CONFIGURATION...................................................................................................308
P
IN
C
ONFIGURATION
—484-B
ALL
HSBGA ................................................................................308
484-B
ALL
HSBGA (56-G6038-002).........................................................................................309
15.1
16.1
PACKAGE INFORMATION ............................................................................................309
DOCUMENT REVISION HISTORY ................................................................................310
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DS26519 16-Port T1/E1/J1 Transceiver
LIST OF FIGURES
Figure 7-1. Block Diagram ......................................................................................................................................... 18
Figure 7-2. Detailed Block Diagram........................................................................................................................... 19
Figure 9-1. SPI Serial Port Access for Read Mode, SPI_CPOL = 0, SPI_CPHA = 0 ............................................... 34
Figure 9-2. SPI Serial Port Access for Read Mode, SPI_CPOL = 1, SPI_CPHA = 0 ............................................... 34
Figure 9-3. SPI Serial Port Access for Read Mode, SPI_CPOL = 0, SPI_CPHA = 1 ............................................... 34
Figure 9-4. SPI Serial Port Access for Read Mode, SPI_CPOL = 1, SPI_CPHA = 1 ............................................... 34
Figure 9-5. SPI Serial Port Access for Write Mode, SPI_CPOL = 0, SPI_CPHA = 0 ............................................... 35
Figure 9-6. SPI Serial Port Access for Write Mode, SPI_CPOL = 1, SPI_CPHA = 0 ............................................... 35
Figure 9-7. SPI Serial Port Access for Write Mode, SPI_CPOL = 0, SPI_CPHA = 1 ............................................... 35
Figure 9-8. SPI Serial Port Access for Write Mode, SPI_CPOL = 1, SPI_CPHA = 1 ............................................... 35
Figure 9-9. Backplane Clock Generation................................................................................................................... 36
Figure 9-10. GPIO Mux Control ................................................................................................................................. 40
Figure 9-11. Device Interrupt Information Flow Diagram........................................................................................... 42
Figure 9-12. IBO Multiplexer Equivalent Circuit—4.096MHz .................................................................................... 47
Figure 9-13. IBO Multiplexer Equivalent Circuit—8.192MHz .................................................................................... 48
Figure 9-14. IBO Multiplexer Equivalent Circuit—16.384MHz .................................................................................. 49
Figure 9-15. RSYNCn Input in H.100 (CT Bus) Mode............................................................................................... 56
Figure 9-16. TSSYNCIOn (Input Mode) Input in H.100 (CT Bus) Mode ................................................................... 56
Figure 9-17. CRC-4 Recalculate Method .................................................................................................................. 80
Figure 9-18. HDLC Message Receive Example........................................................................................................ 86
Figure 9-19. HDLC Message Transmit Example....................................................................................................... 88
Figure 9-20. Network Connection—Longitudinal Protection ..................................................................................... 91
Figure 9-21. T1/J1 Transmit Pulse Templates .......................................................................................................... 94
Figure 9-22. E1 Transmit Pulse Templates ............................................................................................................... 95
Figure 9-23. Receive LIU Termination Options ......................................................................................................... 97
Figure 9-24. Typical Monitor Application ................................................................................................................... 98
Figure 9-25. HPS Block Diagram............................................................................................................................. 101
Figure 9-26. Jitter Attenuation ................................................................................................................................. 102
Figure 9-27. Loopback Diagram .............................................................................................................................. 103
Figure 9-28. Analog Loopback................................................................................................................................. 103
Figure 9-29. Local Loopback ................................................................................................................................... 104
Figure 9-30. Remote Loopback 2 ............................................................................................................................ 104
Figure 9-31. Dual Loopback .................................................................................................................................... 105
Figure 11-1. T1 Receive-Side D4 Timing ................................................................................................................ 268
Figure 11-2. T1 Receive-Side ESF Timing.............................................................................................................. 268
Figure 11-3. T1 Receive-Side Boundary Timing (Elastic Store Disabled)............................................................... 269
Figure 11-4. T1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled).............................................. 269
Figure 11-5. T1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled).............................................. 270
Figure 11-6. T1 Receive-Side Interleave Bus Operation—BYTE Mode.................................................................. 271
Figure 11-7. T1 Receive-Side Interleave Bus Operation—FRAME Mode .............................................................. 272
Figure 11-8. T1 Receive-Side RCHCLKn Gapped Mode During F-Bit.................................................................... 272
Figure 11-9. T1 Transmit-Side D4 Timing ............................................................................................................... 273
Figure 11-10. T1 Transmit-Side ESF Timing........................................................................................................... 273
Figure 11-11. T1 Transmit-Side Boundary Timing (Elastic Store Disabled)............................................................ 274
Figure 11-12. T1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)........................................... 274
Figure 11-13. T1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)........................................... 275
Figure 11-14. T1 Transmit-Side Interleave Bus Operation—BYTE Mode............................................................... 276
Figure 11-15. T1 Transmit-Side Interleave Bus Operation—FRAME Mode ........................................................... 277
Figure 11-16. T1 Transmit-Side TCHCLKn Gapped Mode During F-Bit ................................................................. 277
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