Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Fully Compliant to VAN Specification ISO/11519-3
Handles All Specified Module Types
Handles All Specified Message Types
Handles Retransmission of Frames on Contention and Errors
3 Separate Line Inputs with Automatic Diagnosis and Selection
Normal or Pulsed (Optical and Radio Mode) Coding
VAN Transfer Rate: 1 Mbit/s Maximum
SPI/SCI Interface
– SPI Transfer Rate: 4 Mbit/s Maximum
– SCI Transfer Rate: 125 Kbit/s Maximum
Idle and Sleep Modes
128 Bytes of General-purpose RAM
14 Identifier Registers with All Bits Individually Maskable
6-source Maskable Interrupt, Including an Interrupt-on-reset to Detect Glitches on the
Reset Pin
Integrated Crystal or Resonator Oscillator with Internal Baud Rate Generator and
Buffered Clock Output
Single +5V Power Supply
0.8
µm
CMOS Technology
SO16 Package
VAN Data Link
Controller with
Serial Interface
TSS463-AA
Description
The TSS463AA is a circuit that allows the transfer of all the status information needed
in a car or truck over a single low-cost wire pair, that minimizes electrical wire usage. It
can be used to interconnect powerful functions to control and interface car body elec-
tronics (lights, wipers, power window, etc.).
The TSS463AA is fully compliant with the VAN ISO Standard 11519-3. This standard
supports a wide range of applications such as low-cost remote-controlled switches.
Typically it is used for lamp control, complex, highly-autonomous, distributed systems,
which require fast and secure data transfers.
The TSS463AA is a microprocessor-interfaced line controller for mid- to high-com-
plexity bus-masters and listeners like dashboard controllers, car stereo or mobile
telephone CPUs.
The microprocessor interface consists of a 256-byte RAM and a register area divided
into 11 control registers, 14 channel register sets and 128 bytes of general purpose
RAM, used as a message storage area, and a 6-source maskable interrupt.
The circuit operates in the RAM using DMA techniques, controlled by the channel and
control registers. This allows virtually any microprocessor, including SPI/SCI interface,
to be connected easily to the TSS463AA.
Messages are encoded in enhanced Manchester code, and an optional pulsed code
for use with an optical or radio link, at a maximum bit rate of 1 Mbit/s. The TSS463AA
analyzes the messages received or transmitted according to 6 different criteria includ-
ing some higher level checks.
In addition, the bus interface has three separate inputs with automatic source diagno-
sis and selection. The interface allows for multibus listening or the automatic selection
of the most reliable source at any time if several line receivers are connected to the
same bus.
4205B–AUTO–12/04
1
Application
The TSS463AA is a microprocessor controlled line controller for the VAN bus. It can
interface to virtually any microprocessor which includes SPI or SCI interface.
•
•
•
The TSS463AA provides one full Motorola compatible SPI interface.
It includes one full compatible Intel UART (mode 0 only).
And finally, one 9-bits SCI interface is also integrated.
In addition, the circuit features a single interrupt pin. This pin can be treated as level
sensitive. For example, if there is a pending interrupt inside the circuit when another
interrupt is reset, the INT pin will emit a high pulse with the same pulse width as the
internal write strobe (typically 20 ns).
Figure 1.
Typical Application With Motorola SPI Mode
Remaining pins
SCLK
MOSI
MISO
(2)
PORT X.Y
IRQ
General I/O
(if needed)
100K
MISO
1
SS
INT
2
16
15
SCLK
RESET
(1)
mC
Microcontroller
MOSI
TSS463
3
VDD
4
5
6
14
13
12
11
10
9
RxD0
RxD2
RxD1
VAN Bus
GND
TxD
CKOUT
XTAL1
XTAL2
RESET
(1)
TEST/VSS
7
CKOUT
8
Notes:
1. The TSS463AA RESET pin can either be connected to GND through a 1 µF capaci-
tor, or the µC RESET pin or unconnected (inactive with internal pull-up).
2. Leaving MISO output pin floating in high impedance mode slightly increases standby
consumption. A 100 KΩ pull-up/pull-down resistor is recommended.
4
TSS463-AA
4205B–AUTO–12/04
TSS463-AA
Microprocessor
Interface
Interface Modes
Motorola SPI Mode
The processor controls the TSS463AA by reading and writing the internal registers of
the circuit. These registers appear to the processor as regular memory locations.
The TSS463AA must be connected with an SPI or SCI serial interface. The following
section provides information on switching from one mode to another.
The first two bytes to be sent by the master (CPU) are called “Initialization Sequence”:
This sequence provides a proper asynchronous RESET in the TSS463AA and it selects
the Motorola SPI, Intel SPI or the SCI serial mode. This initialization sequence is shown
on Figure 4. Two 0x00 will cause an internal RESET and assert the Motorola SPI mode,
Two “0xFF” will provide an internal RESET and assert the Intel
®
SPI mode and “9 bits to
0 followed by 0xFF or 0xFE” will generate an internal RESET and assert the 9-bits SCI
mode.
Figure 2.
Mode Configuration Byte
SPI 8 Pulses
SCLK
MOSI
0x00
or 0xFF
0x00
0xFF
Motorola
Intel
SS
Internal RESET
Internal RESET and SPI Mode (Intel or Motorola)
SCI 9 Pulses
SCLK
MOSI
0 . 0000 . 0000
1 . 1 . 1111
111
SS
Internal RESET
Internal RESET and SCI Mode
The Motorola Serial Peripheral Interface (SPI) is fully compatible with the SPI Motorola
protocol. The interface is implemented for slave-mode only (the TSS463AA can not gen-
erate SPI frames by itself).
The SPI interface allows the interconnection of several CPUs and peripherals on the
same printed circuit board.
The SPI mode interface consists of 4 pins: separate wires are required for data and
clock, so the clock is not included in the data stream as shown in Figure 5. One pin is
needed for the serial clock (SCLK), two pins for data communication MOSI and MISO
and one pin for Slave Select (SS).
5
4205B–AUTO–12/04
京公网安备 11010802033920号
EEWORLD
