Features
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8 K
×
8-bit EEPROM
EEPROM Programmable Options
Read Protection for the EEPROM Program Memory
256
×
4-bit RAM
2
×
32
×
16-bit Data EEPROM
Up to Seven External/Internal Interrupt Sources
Eight Hardware and Software Interrupt Priorities
16 Bi-directional I/Os
Wide Supply-voltage Range (1.8V to 6.5V)
Very Low Sleep Current (< 1 µA)
Synchronous Serial Interface (2-wire, 3-wire)
Multifunction Timer/Counter with Prescaler/Interval Timer
Voltage Monitoring Inclusive Lo_BAT Detect
Watchdog, POR and Brown-out Function
8k-flash
Microcontroller
ATAM894
1. Description
The ATAM894 is a member of the Atmel’s family of 4-bit single chip microcontrollers
with 8K
×
8-bit EEPROM program memory. It is based on the 4-K MTP version
ATAM893 and fully compatible with this MTP and the ROM versions ATAR090/890
and ATAR092/892.
Figure 1-1.
Block Diagram
V
SS
V
DD
OSC1 OSC2
Brown-out protect.
RESET
Voltage monitor
External input
VMI
BP10
Port 1
BP13
Data direction
RC
Crystal
oscillators oscillators
External
clock input
UTCM
Timer 1
interval- and
watchdog timer
Timer 2
with prescaler
T2I
T2O
SD
Clock management
EEPROM
8 K x 8 bit
RAM
256 x 4 bit
Modulator 2
SSI
SC
T3O
T3I
BP20/NTE
Port 2
MARC4
4-bit CPU core
I/O bus
Serial interface
Modulator 3
Demodulator
Timer 3
timer/counter
BP21
BP22
BP23
Data direction +
alternate function
Port 4
Data direction +
interrupt control
Port 5
Data dir. +
alt. function
Port 6
EEPROM
2 x 32 x 16 bit
SD
SC
BP40
BP42
BP52
BP50
T2O
INT3
INT6
INT1
SC
BP43
BP51
BP53
BP41
VMI
INT3
INT6
INT1
T2I
SD
BP60
T3O
BP63
T3I
Rev. 4679D–4BMCU–05/05
2. Pin Configuration
Figure 2-1.
Pinning SSO24 Package
NC
NC
VDD
BP40/INT3/SC
1
2
3
4
24
23
22
21
20
19
18
17
16
15
14
13
NC
NC
VSS
BP43/INT3/SD
BP42/T2O
BP41/VMI/T2I
BP23
BP22
BP21
BP20/NTE
BP63/T3I
BP13
BP53/INT1
5
BP52/INT1
6
BP51/INT6
BP50/INT6
7
8
OSC1
9
OSC2
10
BP60/T3O
11
BP10
12
Table 2-1.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Pin Description
Symbol
NC
NC
VDD
BP40
BP53
BP52
BP51
BP50
OSC1
OSC2
BP60
BP10
BP13
BP63
BP20
BP21
BP22
BP23
Type
–
–
–
I/O
I/O
I/O
I/O
I/O
I
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Function
Not connected
Not connected
Supply voltage
Alternate Function
–
–
–
Reset State
–
–
NA
Input
Input
Input
Input
Input
Bi-directional I/O line of Port 4.0 SC-serial clock or INT3 external interrupt input
Bi-directional I/O line of Port 5.3 INT1 external interrupt input
Bi-directional I/O line of Port 5.2 INT1 external interrupt input
Bi-directional I/O line of Port 5.1 INT6 external interrupt input
Bi-directional I/O line of Port 5.0 INT6 external interrupt input
Oscillator input
Oscillator output
4-MHz crystal input or 32-kHz crystal input or external
Input
clock input or external trimming resistor input
4-MHz crystal output or 32-kHz crystal output or
external clock input
Input
Input
Input
Input
Input
Bi-directional I/O line of Port 6.0 T3O Timer 3 output
Bi-directional I/O line of Port 1.0 –
Bi-directional I/O line of Port 1.3 –
Bi-directional I/O line of Port 6.3 T3I Timer 3 input
Bi-directional I/O line of Port 2.0
NTE test mode enable, see section
”Master Reset” on
Input
page 12
Input
Input
Input
Bi-directional I/O line of Port 2.1 –
Bi-directional I/O line of Port 2.2 –
Bi-directional I/O line of Port 2.3 –
2
ATAM894
4679D–4BMCU–05/05
ATAM894
Table 2-1.
Pin
19
20
21
22
23
24
Pin Description (Continued)
Symbol
BP41
BP42
BP43
VSS
NC
NC
Type
I/O
I/O
I/O
–
–
–
Function
Bi-directional I/O line of Port 4.1
Alternate Function
VMI voltage monitor input or T2I external clock input
Timer 2
Reset State
Input
Input
Input
Input
–
–
Bi-directional I/O line of Port 4.2 T2O Timer 2 output
Bi-directional I/O line of Port 4.3 SD serial data I/O or INT3 external interrupt input
Circuit ground
Not connected
Not connected
–
–
–
3. Introduction
The ATAM894 is a member of Atmel’s family of 4-bit single-chip microcontrollers. Instead of
ROM it contains EEPROM, RAM, parallel I/O ports, two 8-bit programmable multifunction
timer/counters, voltage supervisor, interval timer with watchdog function and a sophisticated
on-chip clock generation with integrated RC-, 32-kHz and 4-MHz crystal oscillators.
4. Differences Between ATAM894 and ATARx90/x92
4.1
Program Memory
The program memory of the MTP device is realized as an EEPROM. The memory size for user
programs is 8192 bytes. It is programmed as 258
×
32-byte blocks of data. The implemented
LOCK bit function is user selectable and protects the device from unauthorized read out of the
program memory.
4.2
Configuration Memory
An additional area of 64 bytes of the EEPROM is used to store information about the hardware
configuration. All the options that are selectable for the ROM versions are available to the user.
This includes not only the different port options but also the possibilities to select different capac-
itors for OSC1 and OSC2, the option to enable or disable the hardlock for the watchdog, the
option to select OSC2 instead of OSC1 as external clock input and the option to enable the
external clock monitor as a reset source. Activating the options is performed by the reset cir-
cuitry. Reset starts a download sequence to transfer the information from the memory into a shift
register (configuration register).
4.3
Data Memory
The ATAM894 contains an internal data EEPROM that is organized as two pages of 32
×
16 bit.
If it is necessary to be compatible with the ROM parts, only one page must be used with the
flash part. Also for compatibility reasons the access to the EEPROM is handled via the MCL
(serial interface) as in the corresponding ROM parts. A behavioral difference that only needs to
be considered for error handling can be seen, when the communication via the MCL is not termi-
nated correctly. A missing STOP condition leads to a significantly higher current consumption for
the ROM parts compared to the flash parts. A slightly different concept for the read amplifiers of
the memory makes the flash part more tolerant in terms of communication errors.
3
4679D–4BMCU–05/05
4.4
Reset Function
During each reset (power-on or brown-out) the configuration register is reset and reloaded with
the data from the configuration memory. This leads to a slightly different behavior compared to
the ROM versions. Both devices switch their I/Os to input during reset but the ROM part has the
mask selected pull-up or pull-down resistors active while the MTP has them removed until the
download is finished.
5. MARC4 Architecture
5.1
General Description
The MARC4 microcontroller consists of an advanced stack-based, 4-bit CPU core and on-chip
peripherals. The CPU is based on the Harvard architecture with physically separate program
memory (ROM) and data memory (RAM). Three independent buses, the instruction bus, the
memory bus and the I/O bus, are used for parallel communication between ROM, RAM and
peripherals. This enhances program execution speed by allowing both instruction prefetching,
and a simultaneous communication to the on-chip peripheral circuitry. The extremely powerful
integrated interrupt controller with associated eight prioritized interrupt levels supports fast and
efficient processing of hardware events. The MARC4 is designed for the high-level programming
language qFORTH. The core includes both, an expression and a return stack. This architecture
enables high-level language programming without any loss of efficiency or code density.
Figure 5-1.
MARC4 Core
MARC4 CORE
Reset
Program
memory
PC
X
Y
SP
RP
RAM
256 x 4-bit
Reset
Clock
Instruction
bus
Memory bus
Instruction
decoder
TOS
CCR
Interrupt
controller
I/O bus
ALU
System
clock
Sleep
On-chip peripheral modules
4
ATAM894
4679D–4BMCU–05/05
ATAM894
5.2
Components of MARC4 Core
The core contains ROM, RAM, ALU, program counter, RAM address registers, instruction
decoder and interrupt controller. The following sections describe each functional block in more
detail.
5.2.1
Program Memory
The program memory (EEPROM) is electrically programmable and erasable with the customer
application program. The program memory is addressed by a 12-bit wide program counter and
an additional ROM bank register, thus predefining a maximum linear adressable program bank
size of 4 Kbytes. The upper 2 Kbytes may be exchanged by ROM banking, thus allowing to
address a maximum of 10 Kbytes user program. 8 Kbytes of program memory are available
within the ATAM894. The lowest user (EEP)ROM address segment is taken up by a 512-byte
zero page which contains predefined start addresses for interrupt service routines and special
subroutines accessible with single byte instructions (SCALL).
The corresponding memory map is shown in
Figure 5-2.
Look-up tables of constants can also be
held in ROM and are accessed via the MARC4’s built-in table instruction.
Figure 5-2.
ROM Map
Bank 4
Port D: 11xxb
Bank 3
1FFh
1F8 h
1 F0 h
1E8h
1E0h
1E0h
1C 0h
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INT0
Port D: 10xxb
SCALL addresses
Bank 2
FFFh
Port D: 01xxb
1 8 0h
1 4 0h
Bank 1
Port D: 00xxb
page
100h
0C 0h
080h
800h
7FFh
Base bank
Zero page
000h
000h
020h
01 8 h
01 0 h
008h
000h
0 4 0h
0 0 8h
000h
$RESET
$AUTOSLEEP
5.2.1.1
ROM Banking
For customers programming with qFORTH the bank switching is fully supported by the compiler.
The MARC4 switches from one ROM bank to another by writing the new bank number to the
ROM Bank Register (RBR). Conventional program space (power-up bank) resides in ROM bank
0. Each ROM bank consists of a 2 Kbyte address space whereby the lowest 2 Kbyte, the base
bank, is common to all banks, so that addresses between 000h and 7FFh always access the
same ROM data (see
Figure 5-2).
When ROM banking is used, the compiler will, if necessary,
insert program code to save and restore the condition of the RBR on bank switching.
RAM
The ATAM894 contains 256
×
4-bit wide static random access memory (RAM). It is used for the
expression stack, the return stack and data memory for variables and arrays. The RAM is
addressed by any of the four 8-bit wide RAM address registers SP, RP, X and Y.
5.2.2
5
4679D–4BMCU–05/05
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