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SY100S336A_06: DescriptionENHANCED 4-STAGE COUNTER/SHIFT REGISTER; File Size124KB，10 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com

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ENHANCED 4-STAGE COUNTER/SHIFT REGISTER

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Micrel, Inc.

ENHANCED 4-STAGE

COUNTER/SHIFT REGISTER

SY100S336A

FEATURES

Max. shift frequency of 700MHz

Clock to Q delay max. of 1100ps

to TC speed improved by 50%

set-up and hold time reduced by more than 50%

min. of –170mA

Industry standard 100K ECL levels

Internal 75K

Ω

input pull-down resistors

Extended supply voltage option:

= –4.2V to –5.5V

Voltage and temperature compensation for improved

noise immunity

50% faster than Fairchild 300K at lower power

Function and pinout compatible with Fairchild F100K

Available in 24-pin CERPACK and 28-pin PLCC

packages

DESCRIPTION

The SY100S336A is functionally the same as the

SY100S336, but has S

to TC speed and Sn set-up and

hold times significantly improved, allowing for higher clock

frequency when used as a cascaded multi-stage counter.

The SY100S336A functions either as a modulo-16 up/

down counter or as a 4-bit bidirectional shift register and is

designed for use in high-performance ECL systems. Three

Select inputs (Sn) are provided for determining the mode of

operation. The Function Table lists the available modes of

operation. In order to allow cascading for multistage

counters, two Count Enable controls (CEP, CET) are

provided. The CET input also functions as the Serial Data

input (S

) for a shift-up operation, while the D

input serves

as the Serial Data input for the shift-down operation.

When the device is in the counting mode, the Terminal

Count (TC) goes to a logical LOW when the count reaches

15 for count-up or reaches 0 for count-down. When in the

shift mode, the TC output simply repeats the Q

output.

The flexiblity provided by the TC/Q

output and the D

CET input allows these signals to be interconnected from

one stage to the next higher stage for multistage counting

or shift-up operations. The individual Presets (P

) allow

initialization of the counter by entering data in parallel to

preset the counter. A logic HIGH on the Master Reset (MR)

overrides all other inputs and asynchronously clears the

flip-flops. An additional synchronous Clear is provided, as

well as a complement function which synchronously inverts

the contents of the flip-flops. All inputs have 75KΩ pull-

down resistors.

PIN NAMES

CEP

/CET

— S

EES

CCA

– P

— Q

Function

Clock Pulse Input

Count Enable Parallel Input (Active LOW)

Serial Data Input/Count Enable Trickle

Input (Active LOW)

Select Inputs

Master Reset Input

Substrate

CCO

for ECL Outputs

Preset Inputs

Serial Data Input

Terminal Count Output

Data Outputs

Complementary Data Outputs

M9999-032206

hbwhelp@micrel.com or (408) 955-1690

Rev.: H

Amendment: /0

Issue Date: March 2006

SY100S336A_06 Related Products

	SY100S336A_06	SY100S336AFCTR	SY100S336AJZTR	SY100S336AJZ
Description	ENHANCED 4-STAGE COUNTER/SHIFT REGISTER	ENHANCED 4-STAGE COUNTER/SHIFT REGISTER	ENHANCED 4-STAGE COUNTER/SHIFT REGISTER	ENHANCED 4-STAGE COUNTER/SHIFT REGISTER
Is it Rohs certified?	-	incompatible	conform to	conform to
Maker	-	Microchip	Microchip	Microchip
Parts packaging code	-	QFP	QLCC	QLCC
package instruction	-	QFF, QFL24,.4SQ	QCCJ, LDCC28,.5SQ	QCCJ, LDCC28,.5SQ
Contacts	-	24	28	28
Reach Compliance Code	-	unknow	compli	compli
Other features	-	CAN BE USED AS 4-BIT BIDIRECTIONAL SHIFT REGISTER	CAN BE USED AS 4-BIT BIDIRECTIONAL SHIFT REGISTER	CAN BE USED AS 4-BIT BIDIRECTIONAL SHIFT REGISTER
Counting direction	-	BIDIRECTIONAL	BIDIRECTIONAL	BIDIRECTIONAL
series	-	100S	100S	100S
JESD-30 code	-	S-GQFP-F24	S-PQCC-J28	S-PQCC-J28
JESD-609 code	-	e0	e3	e3
length	-	9.78 mm	11.48 mm	11.48 mm
Load/preset input	-	YES	YES	YES
Logic integrated circuit type	-	BINARY COUNTER	BINARY COUNTER	BINARY COUNTER
Operating mode	-	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Number of digits	-	4	4	4
Number of functions	-	1	1	1
Number of terminals	-	24	28	28
Maximum operating temperature	-	70 °C	70 °C	70 °C
Package body material	-	CERAMIC, GLASS-SEALED	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	-	QFF	QCCJ	QCCJ
Encapsulate equivalent code	-	QFL24,.4SQ	LDCC28,.5SQ	LDCC28,.5SQ
Package shape	-	SQUARE	SQUARE	SQUARE
Package form	-	FLATPACK	CHIP CARRIER	CHIP CARRIER
Peak Reflow Temperature (Celsius)	-	240	260	260
power supply	-	-4.5 V	-4.5 V	-4.5 V
propagation delay (tpd)	-	1.2 ns	1.1 ns	1.1 ns
Certification status	-	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	-	2.29 mm	4.57 mm	4.57 mm
surface mount	-	YES	YES	YES
technology	-	ECL	ECL	ECL
Temperature level	-	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	-	Tin/Lead (Sn/Pb)	Matte Tin (Sn)	Matte Tin (Sn)
Terminal form	-	FLAT	J BEND	J BEND
Terminal pitch	-	1.27 mm	1.27 mm	1.27 mm
Terminal location	-	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
Trigger type	-	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE
width	-	9.78 mm	11.48 mm	11.48 mm
minfmax	-	700 MHz	700 MHz	700 MHz

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