A3995
DMOS Dual Full Bridge PWM Motor Driver
Last Time Buy
This part is in production but has been determined to be
LAST TIME BUY. This classification indicates that the product is
obsolete and notice has been given. Sale of this device is currently
restricted to existing customer applications. The device should not be
purchased for new design applications because of obsolescence in the
near future. Samples are no longer available.
Date of status change: September 3, 2018
Deadline for receipt of LAST TIME BUY orders: June 30, 2019
and for new customers or new applications, refer to the
A5995GEVTR-T.
Recommended Substitutions:
For existing customer transition,
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no respon-
sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
A3995
DMOS Dual Full Bridge PWM Motor Driver
FEATURES AND BENEFITS
▪
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▪
▪
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36 V output rating
2.4 A, DC motor driver
Synchronous rectification
Internal undervoltage lockout (UVLO)
Thermal shutdown circuitry
Crossover-current protection
Very thin profile QFN package
The A3995 is designed to drive two DC motors at currents up to
2.4 A. Capable of drive voltages up to 36 V, the A3995 includes
two independent fixed off-time PWM current regulators that
operate in either fast or slow decay mode, as determined by
the MODE input. Internal synchronous rectification control
circuitry is provided to improve power dissipation during
PWM operation.
Protection features include: thermal shutdown with hysteresis,
undervoltage lockout (UVLO) and crossover current protection.
Special power-up sequencing is not required.
The A3995 is supplied in a 36 pin QFN package (suffix EV)
with exposed power tab for enhanced thermal performance. It
has a 6 mm × 6 mm footprint, with a nominal overall package
height of 0.90 mm, and is lead (Pb) free, with 100% matte tin
leadframe plating.
36-pin QFN
0.90 mm nominal height (suffix EV)
DESCRIPTION
PACKAGE:
Not to scale
Typical Application Diagram
CP1
VDD
CP2
VCP
VBB
VBB
OUT1A
OUT1A
OUT1B
OUT1B
SENSE1
SENSE1
MODE1
PHASE1
Microcontroller or
Controller Logic
ENABLE1
VREF1
MODE2
PHASE2
ENABLE2
VREF2
A3995
OUT2A
OUT2A
OUT2B
OUT2B
GND
GND
GND
A3995DS Rev. 3
MCO-0000501
GND
SENSE2
SENSE2
September 10, 2018
A3995
SELECTION GUIDE
Part Number
A3995SEVTR-T
DMOS Dual Full Bridge PWM Motor Driver
Packing
1500 pieces per reel
ABSOLUTE MAXIMUM RATINGS
Characteristic
Load Supply Voltage
Logic Supply Voltage
Output Current
*
Logic Input Voltage Range
SENSEx Pin Voltage
VREFx Pin Voltage
Operating Temperature Range
Junction Temperature
Storage Temperature Range
Symbol
V
BB
V
DD
I
OUT
V
IN
V
SENSEx
V
REFx
T
A
T
J
(max)
T
stg
Range S
Pulsed t
w
< 1µs
Continuous
Pulsed t
w
< 1µs
Pulsed t
w
< 1 µs
Notes
Rating
–0.5 to 36
38
–0.4 to 7
2.4
3.5
–0.3 to 7
0.5
2.5
2.5
–20 to 85
150
–55 to 150
Units
V
V
V
A
A
V
V
V
V
°C
°C
°C
* May be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a
Junction Temperature of 150°C.
THERMAL CHARACTERISTICS:
May require derating at maximum conditions
Characteristic
Package Thermal Resistance
Symbol
R
θJA
Test Conditions
EV package, 4-layer PCB based on JEDEC standard
Min.
27
Units
°C/W
Power Dissipation versus Ambient Temperature
5500
5000
4500
4000
Power Dissipation, P
D
(mW)
3500
3000
2500
2000
1500
1000
500
0
25
50
75
100
125
Temperature (°C)
150
175
EV Package
4-layer PCB
(R
θJA
= 27 ºC/W)
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
2
A3995
DMOS Dual Full Bridge PWM Motor Driver
Functional Block Diagram
VCP
VBB
VDD
OSC
CHARGE
PUMP
V
CP
DMOS Full Bridge 1
MODE1
PHASE1
ENABLE1
CONTROL
LOGIC
GATE
DRIVE
VBB
CP1
CP1
OUT1A
OUT1A
OUT1B
OUT1B
Sense1
VREF1
3
-
PWM Latch
BLANKING
SENSE1
SENSE1
+
V
CP
DMOS Full Bridge 2
R
S1
MODE2
PHASE2
ENABLE2
CONTROL
LOGIC
GATE
DRIVE
OUT2A
OUT2A
OUT2B
OUT2B
Sense2
VREF2
3
GND
GND
GND
GND
+
-
PWM Latch
BLANKING
Sense2
SENSE2
SENSE2
NC
NC
NC
NC
NC
NC
R
S2
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
3
A3995
DMOS Dual Full Bridge PWM Motor Driver
ELECTRICAL CHARACTERISTICS
[1]
: Valid at T
A
= 25°C, V
BB
= 36 V, unless otherwise noted
Characteristics
Load Supply Voltage Range
Logic Supply Voltage Range
VDD Supply Current
Output On Resistance
V
f
, Outputs
Output Leakage
VBB Supply Current
CONTROL LOGIC
Logic Input Voltage
Logic Input Current
Input Hysteresis
V
IN(1)
V
IN(0)
I
IN
V
hys
PWM change to source on
Propagation Delay Times
t
pd
PWM change to source off
PWM change to sink on
PWM change to sink off
Crossover Delay
Blank Time
VREFx Pin Input Voltage Range
VREFx Pin Reference Input Current
PROTECTION CIRCUITS
VBB UVLO Threshold
VBB Hysteresis
VDD UVLO Threshold
VDD Hysteresis
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
[1]
For
[2]
Typical
Symbol
V
BB
V
DD
I
DD
R
DS(on)
Operating
Operating
Test Conditions
Min.
8.0
3.0
–
–
–
–
–20
–
Typ.
[2]
–
–
7
350
350
–
–
–
Max.
36
5.5
10
450
450
1.3
20
8
Units
V
V
mA
mΩ
mΩ
V
µA
mA
Source driver, I
OUT
= –1.2 A, T
J
= 25°C
Sink driver, I
OUT
= 1.2 A, T
J
= 25°C
I
OUT
= 1.2 A
Outputs, V
OUT
= 0 to V
BB
I
OUT
= 0 mA, outputs on, f
PWM
= 50 kHz,
DC = 50%
I
DSS
I
BB
0.7 × V
DD
–
V
IN
= 0 to 5 V
–20
150
350
35
350
35
300
2.5
Operating
V
REF
= 1.5
V
BB
rising
V
DD
rising
0.0
–
7.3
400
2.65
75
155
–
–
–
<1.0
300
550
–
550
–
425
3.2
–
–
7.6
500
2.8
105
165
15
–
0.3 × V
DD
20
500
1000
300
1000
250
1000
4
1.5
±1
7.9
600
2.95
125
175
–
V
V
µA
mV
ns
ns
ns
ns
ns
µs
V
μA
V
mV
V
mV
°C
°C
t
COD
t
BLANK
V
REFx
I
REF
V
UV(VBB)
V
UV(VBB)hys
V
UV(VDD)
V
UV(VDD)hys
T
JTSD
T
JTSDhys
input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for indi-
vidual units, within the specified maximum and minimum limits.
[3]
V
ERR
= [(V
REF
/3) – V
SENSE
] / (V
REF
/3).
DC Control Logic
PHASE
ENABLE
1
1
1
1
0
1
0
1
X
0
1
0
0
0
MODE
1
0
1
0
1
0
0
OUTA
H
H
L
L
L
L
H
OUTB
L
L
H
H
L
H
L
Forward (slow decay SR)
Forward (fast decay SR)
Reverse (slow decay SR)
Reverse (fast decay SR)
Brake (slow decay SR)
Fast decay SR*
Fast decay SR*
Function
* To prevent reversal of current during fast decay SR – the outputs will go to the high impedance state as the current gets near zero.
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
4
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