ADM6996F datasheet, PDF - EEWORLD Datasheet

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ADM6996F: Description6 port 10/100 Mb/s Single Chip Ethernet Switch Controller; CategoryThe embedded processor and controller Microcontrollers and processors; File Size640KB，69 Pages; ManufacturerInfineon; Websitehttp://www.infineon.com/

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ADM6996F Overview

6 port 10/100 Mb/s Single Chip Ethernet Switch Controller

ADM6996F Parametric

Parameter Name	Attribute value
Maker	Infineon
Parts packaging code	QFP
package instruction	PLASTIC, QFP-128
Contacts	128
Reach Compliance Code	compli
Other features	ALSO REQUIRES 3.3V SUPPLY
boundary scan	NO
maximum clock frequency	25 MHz
Data encoding/decoding methods	NRZ; NRZI; BIPH-LEVEL(MANCHESTER)
Maximum data transfer rate	12.5 MBps
JESD-30 code	R-PQFP-G128
length	20 mm
low power mode	NO
Number of serial I/Os	7
Number of terminals	128
Package body material	PLASTIC/EPOXY
encapsulated code	FQFP
Package shape	RECTANGULAR
Package form	FLATPACK, FINE PITCH
Certification status	Not Qualified
Maximum seat height	3.4 mm
Maximum supply voltage	1.9 V
Minimum supply voltage	1.7 V
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
width	14 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, LAN

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An Infineon Technologies Company

ADM6996F

6 port 10/100 Mb/s

Single Chip Ethernet Switch Controller

Data Sheet

Version 1.02

Infineon-ADMtek Co Ltd

Information in this document is provided in connection with Infineon-ADMtek Co Ltd products. Infineon-

ADMtek Co Ltd may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved”

or “undefined”. Infineon-ADMtek Co Ltd reserves these for future definition and shall have no

responsibility whatsoever for conflicts or incompatibilities arising from future changes to them

The products may contain design defects or errors known as errata, which may cause the product to deviate

from published specifications. Current characterized errata are available on request. To obtain latest

documentation please contact you local Infineon-ADMtek Co Ltd sales office or visit Infineon-ADMtek Co

Ltd’s website at

http://www.admtek.com.tw

*Third-party brands and names are the property of their respective owners.

Copyright

V1.03

Table of Contents

Chapter 1 Product Overview ........................................................................................ 1-1

1.1

Overview.......................................................................................................... 1-1

1.2

Features ............................................................................................................ 1-2

1.3

Applications ..................................................................................................... 1-2

1.4

Block Diagram ................................................................................................. 1-3

1.5

Abbreviations................................................................................................... 1-3

1.6

Conventions ..................................................................................................... 1-5

1.6.1

Data Lengths............................................................................................ 1-5

1.6.2

Pin Types.................................................................................................. 1-5

1.6.2

Chapter 2 Interface Description ................................................................................... 2-1

2.1

Pin Diagram ..................................................................................................... 2-1

2.2

Pin Description by Function ............................................................................ 2-2

2.2.1

Twisted Pair Interface.............................................................................. 2-2

2.2.2

5th Port (MII) Interfaces.......................................................................... 2-2

2.2.3

6th Port (MII) Interfaces.......................................................................... 2-3

2.2.4

LED Interface........................................................................................... 2-5

2.2.5

EEPROM/Management Interface ............................................................ 2-6

2.2.6

Power/Ground, 48 pins............................................................................ 2-6

2.2.7

Miscellaneous .......................................................................................... 2-6

Chapter 3 Function Description ................................................................................... 3-1

3.1

Functional Descriptions ................................................................................... 3-1

3.2

10/100M PHY Block ....................................................................................... 3-1

3.3

100Base-X Module .......................................................................................... 3-1

3.4

100Base-X Receiver ........................................................................................ 3-2

3.4.1

A/D Converter.......................................................................................... 3-2

3.4.2

Adaptive Equalizer and timing Recovery Module ................................... 3-2

3.4.3

NRZI/NRZ and Serial/Parallel Decoder.................................................. 3-2

3.4.4

Data De-scrambling................................................................................. 3-3

3.4.5

Symbol Alignment .................................................................................... 3-3

3.4.6

Symbol Decoding ..................................................................................... 3-3

3.4.7

Valid Data Signal..................................................................................... 3-3

3.4.8

Receive Errors ......................................................................................... 3-4

3.4.9

100Base-X Link Monitor.......................................................................... 3-4

3.4.10

Carrier Sense ........................................................................................... 3-4

3.4.11

Bad SSD Detection................................................................................... 3-4

3.4.12

Far-End Fault .......................................................................................... 3-5

3.5

100Base-TX Transceiver ................................................................................. 3-5

3.5.1

Transmit Drivers...................................................................................... 3-5

3.5.2

Twisted-Pair Receiver.............................................................................. 3-5

3.6

10Base-T Module............................................................................................. 3-5

3.6.1

Operation Modes ..................................................................................... 3-6

3.6.2

Manchester Encoder/Decoder ................................................................. 3-6

3.6.3

Transmit Driver and Receiver ................................................................. 3-6

3.6.4

Smart Squelch .......................................................................................... 3-6

ADM6996F

3.7

Carrier Sense.................................................................................................... 3-7

3.8

Jabber Function................................................................................................ 3-7

3.9

Link Test Function........................................................................................... 3-7

3.10

Automatic Link Polarity Detection.............................................................. 3-8

3.11

Clock Synthesizer ........................................................................................ 3-8

3.12

Auto Negotiation.......................................................................................... 3-8

3.13

Memory Block ............................................................................................. 3-8

3.14

Switch Functional Description..................................................................... 3-9

3.15

Basic Operation............................................................................................ 3-9

3.15.1

Address Learning ..................................................................................... 3-9

3.15.2

Address Recognition and Packet Forwarding ....................................... 3-10

3.15.3

Address Aging ........................................................................................ 3-10

3.15.4

Back off Algorithm ................................................................................. 3-10

3.15.5

Inter-Packet Gap (IPG) ......................................................................... 3-10

3.15.6

Illegal Frames........................................................................................ 3-11

3.15.7

Half Duplex Flow Control ..................................................................... 3-11

3.15.8

Full Duplex Flow Control...................................................................... 3-11

3.15.9

Broadcast Storm filter............................................................................ 3-11

3.16 Auto TP MDIX function................................................................................ 3-11

3.17

Port Locking............................................................................................... 3-12

3.18

VLAN setting & Tag/Untag & port-base VLAN ...................................... 3-12

3.19

Priority Setting ........................................................................................... 3-13

3.20

LED Display .............................................................................................. 3-13

Chapter 4 Register Description .................................................................................... 4-1

4.1

EEPROM Content............................................................................................ 4-1

4.2

EEPROM Register Map................................................................................... 4-1

4.3

EEPROM Register ........................................................................................... 4-2

4.3.1

Signature Register, offset: 0x00h.............................................................. 4-2

4.3.2

Configuration Registers, offset: 0x01h ~ 0x09h ...................................... 4-3

4.3.3

Reserved Register, offset: 0x0ah.............................................................. 4-3

4.3.4

Configuration Register, offset: 0x0bh...................................................... 4-4

4.3.5

Reserved Register, offset: 0x0ch~0x0dh .................................................. 4-4

4.3.6

VLAN priority Map Register, offset: 0x0eh ............................................. 4-4

4.3.7

TOS priority Map Register, offset: 0x0fh................................................. 4-4

4.3.8

Packet with Priority: Normal packet content .......................................... 4-5

4.3.9

VLAN Packet............................................................................................ 4-5

4.3.10

TOS IP Packet.......................................................................................... 4-1

4.3.11

Miscellaneous Configuration Register, offset: 0x10h.............................. 4-1

4.3.12

VLAN mode select Register, offset: 0x11h............................................... 4-2

4.3.13

Miscellaneous Configuration register, offset: 0x12h .............................. 4-4

4.3.14

VLAN mapping table registers, offset: 0x22h ~ 0x13h ............................ 4-4

4.3.15 Reserved Register, offset: 0x27h ~ 0x23h................................................ 4-4

4.3.16 Port0, 1 PVID bit 11 ~ 4 Configuration Register, offset: 0x28h ............. 4-1

4.3.17 Port2, 3 PVID bit 11 ~ 4 Configuration Register, offset: 0x29h ............. 4-1

4.3.18 Port4, 5 PVID bit 11~4 Configuration Register, offset: 0x2ah ............... 4-1

4.3.19

Port6, 7 PVID bit 11~4 Configuration Register, offset: 0x2bh ............... 4-1

V1.03

ADM6996F

4.3.20

Port8 PVID bit 11~4 & VLAN group shift bits Configuration Register.. 4-1

4.3.21

Reserved Register, offset: 0x2dh.............................................................. 4-2

4.3.22

Reserved Register, offset: 0x2eh .............................................................. 4-2

4.3.23

PHY Restart, offset: 0x2fh........................................................................ 4-2

4.3.24

Miscellaneous Configuration Register, offset: 0x30h.............................. 4-2

4.3.25 Bandwidth Control Register0~3, offset: 0x31h........................................ 4-3

4.3.26 Bandwidth Control Register 4~5, offset: 0x32h....................................... 4-3

4.3.27 Bandwidth Control Enable Register, offset: 0x33h .................................. 4-4

4.4

EEPROM Access ............................................................................................. 4-4

4.5

Serial Register Map.......................................................................................... 4-6

4.6

Serial Register Description .............................................................................. 4-7

4.6.1

Chip Identifier Register, offset: 0x00h..................................................... 4-7

4.6.2

Port Status 0 Register, offset: 0x01h ....................................................... 4-7

4.6.3

Port Status 1 Register, offset: 0x02h ....................................................... 4-9

4.6.4

Cable Broken Status Register, offset: 0x03h............................................ 4-9

4.6.5

Over Flow Flag 0 Register, offset: 0x3ah.............................................. 4-10

4.6.6

Over Flow Flag 0: Register 0x3bh ........................................................ 4-10

4.6.7

Over Flow Flag 2 Register, offset: 0x3ch.............................................. 4-11

4.7

Serial Interface Timing .................................................................................... 4-1

4.8

PHY Register Description................................................................................ 4-2

4.8.1

Control Register, offset: 0x00 .................................................................. 4-2

4.8.2

Status Register, offset: 0x01..................................................................... 4-4

4.8.3

PHY Identifier Register, offset: 0x02 ....................................................... 4-5

4.8.4

PHY Identifier Register, offset: 0x03 ....................................................... 4-5

4.8.5

Auto Negotiation Advertisement Register, offset : 0x04 .......................... 4-6

4.8.6

Auto Negotiation Link Partner Ability Register, offset: 0x05.................. 4-7

4.8.7

Auto Negotiation Expansion Register, offset: 0x06 ................................. 4-7

4.8.8

Next Page Transmit Register, offset: 0x07 ............................................. 4-8

4.8.9

Link Partner Next Page Register, offset: 0x08 ........................................ 4-8

Chapter 5 Electrical Specification................................................................................ 5-1

5.1

TX/FX Interface............................................................................................... 5-1

5.1.1

TP Interface ............................................................................................. 5-1

5.1.2

FX Interface ............................................................................................. 5-1

5.2

DC Characteristics ........................................................................................... 5-2

5.2.1

Absolute Maximum Rating....................................................................... 5-2

5.2.2

Recommended Operating Conditions ...................................................... 5-2

5.2.3

DC Electrical Characteristics for 3.3V Operation .................................. 5-2

5.3

AC Characteristics ........................................................................................... 5-3

5.3.1

Power On Reset........................................................................................ 5-3

5.3.2

EEPROM Interface Timing...................................................................... 5-3

5.3.3

10Base-TX MII Input Timing ................................................................... 5-4

5.3.4

10Base-TX MII Output Timing ................................................................ 5-4

5.3.5

100Base-TX MII Input Timing ................................................................. 5-5

5.3.6

100Base-TX MII Output Timing .............................................................. 5-5

5.3.7

SMI Timing............................................................................................... 5-6

5.3.8

GPSI(7-wire) Input Timing ...................................................................... 5-6

V1.03

ADM6996F

iii

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