CY7C1314BV18-300BZI datasheet, PDF

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CY7C1314BV18-300BZI: DescriptionQDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-165; Categorystorage storage; File Size256KB，25 Pages; ManufacturerCypress Semiconductor

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CY7C1314BV18-300BZI Overview

QDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-165

CY7C1314BV18-300BZI Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Cypress Semiconductor
Parts packaging code	BGA
package instruction	13 X 15 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-165
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	300 MHz
I/O type	SEPARATE
JESD-30 code	R-PBGA-B165
JESD-609 code	e0
length	15 mm
memory density	18874368 bit
Memory IC Type	QDR SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	165
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	512KX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	220
power supply	1.5/1.8,1.8 V
Certification status	Not Qualified
Maximum seat height	1.4 mm
Maximum standby current	0.485 A
Minimum standby current	1.7 V
Maximum slew rate	1.58 mA
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	13 mm
Base Number Matches	1

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PRELIMINARY

CY7C1310BV18

CY7C1312BV18

CY7C1314BV18

18-Mbit QDR-II™ SRAM 2-Word

Burst Architecture

Features

• Separate Independent Read and Write data ports

•

— Supports concurrent transactions

300-MHz clock for high bandwidth

2-Word Burst on all accesses

Double Data Rate (DDR) interfaces on both Read and

Write ports (data transferred at 600 MHz) @ 300 MHz

Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

Functional Description

The CY7C1310BV18, CY7C1910BV18, CY7C1312BV18, and

CY7C1314BV18 are 1.8V Synchronous Pipelined SRAMs,

equipped with QDR™-II architecture. QDR-II architecture

consists of two separate ports to access the memory array.

The Read port has dedicated Data Outputs to support Read

operations and the Write Port has dedicated Data Inputs to

support Write operations. QDR-II architecture has separate

data inputs and data outputs to completely eliminate the need

to “turn-around” the data bus required with common I/O

devices. Access to each port is accomplished through a

common address bus. The Read address is latched on the

rising edge of the K clock and the Write address is latched on

the rising edge of the K clock. Accesses to the QDR-II Read

and Write ports are completely independent of one another. In

order to maximize data throughput, both Read and Write ports

are equipped with Double Data Rate (DDR) interfaces. Each

address location is associated with two 8-bit words

(CY7C1310BV18) or 9-bit words (CY7C1910BV18) or 18-bit

words (CY7C1312BV18) or 36-bit words (CY7C1314BV18)

that burst sequentially into or out of the device. Since data can

be transferred into and out of the device on every rising edge

of both input clocks (K and K and C and C), memory bandwidth

is maximized while simplifying system design by eliminating

bus “turn-arounds.”

Depth expansion is accomplished with Port Selects for each

port. Port selects allow each port to operate independently.

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

• Two output clocks (C and C) accounts for clock skew

and flight time mismatching

• Echo clocks (CQ and CQ) simplify data capture in

high-speed systems

• Single multiplexed address input bus latches address

inputs for both Read and Write ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• Available in x8, x9, x18, and x36 configurations

• Full data coherency, providing most current data

• Core V

= 1.8V (±0.1V); I/O V

DDQ

= 1.4V to V

• 13 x 15 x 1.4 mm 1.0-mm pitch FBGA package, 165 ball

(11x15 matrix)

• Offered in both lead-free and non-lead free packages

• Variable drive HSTL output buffers

• JTAG 1149.1 compatible test access port

• Delay Lock Loop (DLL) for accurate data placement

Configurations

CY7C1310BV18 – 2M x 8

CY7C1910BV18 – 2M x 9

CY7C1312BV18 – 1M x 18

CY7C1314BV18 – 512K x 36

Cypress Semiconductor Corporation

Document #: 38-05619 Rev. *A

•

3901 North First Street

•

San Jose

CA 95134

•

408-943-2600

Revised September 17, 2004

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