K7J321882M-FI250 datasheet, PDF

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K7J321882M-FI250: DescriptionDDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165; Categorystorage storage; File Size339KB，20 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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K7J321882M-FI250 Overview

DDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165

K7J321882M-FI250 Parametric

Parameter Name	Attribute value
Maker	SAMSUNG
Parts packaging code	BGA
package instruction	LBGA,
Contacts	165
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165
length	17 mm
memory density	37748736 bit
Memory IC Type	DDR SRAM
memory width	18
Number of functions	1
Number of terminals	165
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	2MX18
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	1.4 mm
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	15 mm
Base Number Matches	1

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K7J323682M

K7J321882M

Document Title

1Mx36 & 2Mx18 DDR II SIO b2 SRAM

1Mx36-bit, 2Mx18-bit DDR II SIO b2 SRAM

Revision History

Rev. No.

0.0

0.1

History

1. Initial document.

1. Pin name change from DLL to Doff

2. Update JTAG test conditions.

3. Reserved pin for high density name change from NC to Vss/SA

4. Delete AC test condition about Clock Input timing Reference Level

5. Delete clock description on page 2 and add HSTL I/O comment

6. Deleted R/W control pin description on page 2

1. Update current characteristics in DC electrical characteristics

2. Change AC timing characteristics

3. Update JTAG instruction coding and diagrams

1. Add AC electrical characteristics.

2. Change AC timing characteristics.

3. Change DC electrical characteristics(I

SB1

)

1. Change the data Setup/Hold time.

2. Change the Access Time.(tCHQV, tCHQX, etc.)

3. Change the Clock Cycle Time.(MAX value of tKHKH)

4. Change the JTAG instruction coding.

1. Change the Boundary scan exit order.

2. Change the AC timing characteristics(-25, -20)

3. Correct the Overshoot and Undershoot timing diagrams.

1. Change the JTAG Block diagram

1. Correct the JTAG ID register definition

2. Correct the AC timing parameter (delete the tKHKH Max value)

1. Change the Maximum Clock cycle time.

2. Correct the 165FBGA package ball size.

1. Final spec release

1. Delete the x8 Org. part

1. Change the operating current parameter

before

after

Isb1

-25 :

230

250

-20 :

200

230

-16 :

190

220

Draft Date

July, 15 2001

Dec, 14 2001

Remark

Advance

Preliminary

0.2

July, 29. 2002

Preliminary

0.3

Sep. 6. 2002

Preliminary

0.4

Oct. 7. 2002

Preliminary

0.5

Dec. 16, 2002

Preliminary

0.6

0.7

Dec. 26, 2002

Mar. 20, 2003

Preliminary

0.8

April. 4, 2003

Preliminary

1.0

2.0

2.1

Oct. 31, 2003

Dec. 1, 2003

Dec. 13, 2004

Final

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the

specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-

tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

-1-

Dec. 2004

Rev 2.1

K7J323682M

K7J321882M

GENERAL DESCRIPTION

1Mx36 & 2Mx18 DDR II SIO b2 SRAM

The K7J323682M and K7J321882M are 37,748,736-bits DDR Separate I/O

Synchronous Pipelined Burst SRAMs.

They are organized as 1,048,576 words by 36bits for K7J323682M and 2,097,152 words by 18 bits for K7J321882M.

The DDR SIO operation is possible by supporting DDR read and write operations through separate data output and input ports.

Memory bandwidth is higher than DDR sram without separate input output as separate read and write ports

eliminate bus turn around cycle.

Address, data inputs, and all control signals are synchronized to the input clock ( K or K ).

Normally data outputs are synchronized to output clocks ( C and C ), but when C and C are tied high,

the data outputs are synchronized to the input clocks ( K and K ).

Read data are referenced to echo clock ( CQ or CQ ) outputs.

Read address and write address are registered on rising edges of the input K clocks.

Common address bus is used to access address both for read and write operations.

The internal burst counter is fiexd to 2-bit sequential for both read and write operations.

Synchronous pipeline read and late write enable high speed operations.

Simple depth expansion is accomplished by using LD for port selection.

Byte write operation is supported with BW

and BW

( BW

and BW

pins for x18 ( x36 ) device.

Nybble write operation is supported with NW

and NW

pins for x8 device.

IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoriing package pads attachment status with system.

The K7J323682M and K7J321882M are implemented with SAMSUNG's high performance 6T CMOS technology

and is available in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.

Read Operations

Read cycles are initiated by initiating R/W as high at the rising edge of the positive input clock K.

Address is presented and stored in the read address register synchronized with K clock.

For 2-bit burst DDR operation, it will access two 36-bit or 18-bit or 8-bit data words with each read command.

The first pipelined data is transfered out of the device triggered by C clock following next K clock rising edge.

Next burst data is triggered by the rising edge of following C clock rising edge.

Continuous read operations are initated with K clock rising edge.

And pipelined data are transferred out of device on every rising edge of both C and C clocks.

In case C and C tied to high, output data are triggered by K and K insted of C and C.

When the LD is disabled after a read operation, the K7J323682M and K7J321882M will first complete

burst read operation before entering into deselect mode at the next K clock rising edge.

Then output drivers disabled automatically to high impedance state.

Echo clock operation

To assure the output tracibility, the SRAM provides the output Echo clock, pair of compliment clock CQ and CQ,

which are synchronized with internal data output.

Echo clocks run free during normal operation.

The Echo clock is triggered by internal output clock signal, and transfered to external through same structures

as output driver.

Power-Up/Power-Down Supply Voltage Sequencing

The following power-up supply voltage application is recommended: V

, V

DDQ

, V

REF

, then V

. V

and V

DDQ

can be applied

simultaneously, as long as V

DDQ

does not exceed V

by more than 0.5V during power-up. The following power-down supply voltage

removal sequence is recommended: V

, V

REF

, V

DDQ

, V

. V

and V

DDQ

can be removed simultaneously, as long as V

DDQ

does not exceed V

by more than 0.5V during power-down.

-5-

Dec. 2004

Rev 2.1

K7J321882M-FI250 Related Products

	K7J321882M-FI250	K7J323682M-FC250	K7J323682M-FC200	K7J321882M-FC250	K7J321882M-FC200	K7J323682M-FC160
Description	DDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165	DDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165	DDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165	DDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165	DDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165	DDR SRAM, 1MX36, 0.5ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165
Maker	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG
Parts packaging code	BGA	BGA	BGA	BGA	BGA	BGA
package instruction	LBGA,	LBGA,	LBGA,	LBGA,	LBGA,	LBGA,
Contacts	165	165	165	165	165	165
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Maximum access time	0.45 ns	0.45 ns	0.45 ns	0.45 ns	0.45 ns	0.5 ns
Other features	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165
length	17 mm	17 mm	17 mm	17 mm	17 mm	17 mm
memory density	37748736 bit	37748736 bit	37748736 bit	37748736 bit	37748736 bit	37748736 bit
Memory IC Type	DDR SRAM	DDR SRAM	DDR SRAM	DDR SRAM	DDR SRAM	DDR SRAM
memory width	18	36	36	18	18	36
Number of functions	1	1	1	1	1	1
Number of terminals	165	165	165	165	165	165
word count	2097152 words	1048576 words	1048576 words	2097152 words	2097152 words	1048576 words
character code	2000000	1000000	1000000	2000000	2000000	1000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	70 °C	70 °C	70 °C	70 °C	70 °C
organize	2MX18	1MX36	1MX36	2MX18	2MX18	1MX36
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LBGA	LBGA	LBGA	LBGA	LBGA	LBGA
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.4 mm	1.4 mm	1.4 mm	1.4 mm	1.4 mm	1.4 mm
Maximum supply voltage (Vsup)	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
surface mount	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
width	15 mm	15 mm	15 mm	15 mm	15 mm	15 mm
Base Number Matches	1	1	1	1	1	1

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