SY89846U
1.5GHz Precision, LVPECL 1:5 Fanout with 2:1
MUX and Fail Safe Input with Internal
Termination
General Description
The SY89846U is a 2.5/3.3V, 1:5 LVPECL fanout
buffer with a 2:1 differential input multiplexer (MUX).
A unique Fail-Safe Input (FSI) protection prevents
metastable output conditions when the selected
input clock fails to a DC voltage (voltage between
the pins of the differential input drops significantly
below 100mV).
The differential input includes Micrel’s unique, 3-pin
internal termination architecture that can interface to
any differential signal (AC- or DC-coupled) as small
as 100mV (200mV
PP
) without any level shifting or
termination resistor networks in the signal path. The
outputs are 800mV, LVPECL with fast rise/fall times
guaranteed to be less than 250ps.
The SY89846U operates from a 2.5V ±5% or 3.3V
±10% supply and is guaranteed over the full
industrial temperature range of –40°C to +85°C. The
SY89846U is part of Micrel’s high-speed, Precision
Edge
®
product line.
All support documentation can be found on Micrel’s
web site at:
www.micrel.com.
Precision Edge
®
Features
•
Selects between two inputs, and provides 5 precision
LVPECL copies
•
Fail-Safe Input
– Prevents outputs from oscillating when input is
invalid
•
Guaranteed AC performance over temperature and
supply voltage:
– DC-to >1.5GHz throughput
– < 900ps Propagation Delay (IN-to-Q)
– < 250ps Rise/Fall times
•
Ultra-low jitter design:
– <1ps
RMS
random jitter
– <1ps
RMS
cycle-to-cycle jitter
– <10ps
PP
total jitter (clock)
– <0.7ps
RMS
MUX crosstalk induced jitter
•
Unique, patented MUX input isolation design
minimizes adjacent channel crosstalk
•
Unique patented internal termination and VT pin
accepts DC- and AC-coupled inputs (CML, PECL,
LVDS)
•
Wide input voltage range. VCC to GND
•
2.5V ±5% or 3.3 ±10% supply voltage
•
-40°C to +85°C industrial temperature range
•
Available in 32-pin (5mm x 5mm) MLF
®
package
Functional Block Diagram
Applications
•
Fail-safe clock protection
•
SONET clock distribution
•
Backplane distribution
Markets
•
•
•
•
LAN/WAN
Enterprise servers
ATE
Test and measurement
Precision Edge is a registered trademark of Micrel, Inc.
MLF and
MicroLeadFrame
are registered trademarks of Amkor Technology
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
March 2007
M9999-031307-B
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89846U
Ordering Information
(1)
Part Number
SY89846UMG
SY89846UMGTR
(2)
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC Electricals Only.
2. Tape and Reel.
Package
Type
MLF-32
MLF-32
Operating
Range
Industrial
Industrial
Package Marking
SY89846U with
Pb-Free bar-line Indicator
SY89846U with
Pb-Free bar-line Indicator
Lead
Finish
NiPdAu
Pb-Free
NiPdAu
Pb-Free
Pin Configuration
32-Pin MLF
®
(MLF-32)
March 2007
2
M9999-031307-A
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89846U
Pin Description
Pin Number
1,8
Pin Name
VT0, VT1
Pin Function
Input Termination Center-Tap: Each side of a differential input pair terminates to
the VT pin. The VT pin provides a center-tap for each input (IN, /IN) to a
termination network for maximum interface flexibility. See “Input Interface
Applications” subsection.
Differential Inputs: These input pairs are the differential signal inputs to the
device. These inputs accept AC- or DC-coupled signals as small as 100mV. The
input pairs internally terminate to a VT pin through 50Ω. Each input has level
shifting resistors of 3.72kΩ to VCC. This allows a wide input voltage range from
VCC to GND. See Figure 3a, Simplified Differential Input Stage for details. Note
that these inputs will default to a valid (either HIGH or LOW) state if left open.
See “Input Interface Applications” subsection.
Ground. Exposed pad must be connected to a ground plane that is the same
potential as the ground pins.
Single-Ended Input: This TTL/CMOS input disables and enables the Q0-Q4
outputs. It is internally connected to a 25kΩ pull-up resistor and will default to a
logic HIGH state if left open. When disabled, Q goes LOW and /Q goes HIGH.
OE being synchronous, outputs will be enabled/disabled following a rising and a
falling edge of the input clock. V
TH
= V
CC
/2.
Single-Ended Input: This single-ended TTL/CMOS-compatible input selects the
inputs to the multiplexer. Note that this input is internally connected to a 25kΩ
pull-up resistor and will default to logic HIGH state if left open. V
TH
= V
CC
/2.
Reference Voltage: These outputs bias to V
CC
–1.2V. They are used for AC-
coupling inputs IN and /IN. Connect VREF-AC directly to the corresponding VT
pin. Bypass with 0.01µF low ESR capacitor to VCC. Due to limited drive
capability, the VREF-AC pin is only intended to drive its respective VT pin.
Maximum sink/source current is ±0.5mA. See “Input Interface Applications”
subsection.
Positive Power Supply: Bypass with 0.1µF||0.01µF low ESR capacitors as close
to the V
CC
pins as possible.
LVPECL Differential Output Pairs: Differential buffered output copies of the
selected input signal. The output swing is typically 800mV. Unused output pairs
may be left floating with no impact on jitter. See “LVPECL Output Termination”
subsection. Normally terminated with 50Ω to V
CC
-2V. These differential LVPECL
outputs are a logic function of the IN0, IN1, and SEL inputs. See “Truth Table”
below.
2, 3
6, 7
IN0, /IN0
IN1, /IN1
10, 11, 30, 31
GND,
Exposed Pad
4
OE
5
SEL
9, 32
VREF-AC1
VREF-AC0
12, 13, 16, 19,
22, 25, 28, 29
27, 26
24, 23
21, 20
18, 17
15, 14
VCC
Q0, /Q0
Q1, /Q1
Q2, /Q2
Q3, /Q3
Q4, /Q4
Truth Table
Inputs
IN0
0
1
X
X
/IN0
1
0
X
X
IN1
X
X
0
1
/IN1
X
X
1
0
SEL
0
0
1
1
Outputs
Q
0
1
0
1
/Q
1
0
1
0
March 2007
3
M9999-031307-A
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89846U
Absolute Maximum Ratings
(1)
Supply Voltage (V
CC
) .......................... –0.5V to +4.0V
Input Voltage (V
IN
) ..................................–0.5V to V
CC
LVPECL Output Current (I
OUT
)
Continuous ................................................. 50mA
Surge........................................................ 100mA
Current (V
T
)
Source or sink on VT pin........................ ±100mA
Input Current
Source or sink current on (IN, /IN) ........... ±50mA
Current (V
REF
)
Source or sink current on V
REF-AC(4)
......... ±0.5mA
Maximum operating Junction Temperature .....125°C
Lead Temperature (soldering, 20sec.) .............260°C
Storage Temperature (T
s
)................–65°C to +150°C
Operating Ratings
(2)
Supply Voltage (V
CC
) ..................+2.375V to +2.625V
.....................................................+3.0V to +3.6V
Ambient Temperature (T
A
)................ –40°C to +85°C
Package Thermal Resistance
(3)
MLF
®
(θ
JA
)
Still-Air ..................................................... 50°C/W
MLF
®
(ψ
JB
)
Junction-to-Board .................................... 31°C/W
DC Electrical Characteristics
(5)
T
A
= –40°C to +85°C, unless otherwise stated.
Symbol
V
CC
I
CC
R
IN
R
DIFF_IN
V
IH
V
IL
V
IN
V
DIFF_IN
V
IN_FSI
V
REF-AC
V
T_IN
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is
not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB.
θ
JA
and
ψ
JB
values are determined for a 4-layer board in still air unless otherwise stated.
4. Due to the limited drive capability, use for input of the same package only.
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6. V
IN
(max) is specified when V
T
is floating.
Parameter
Power Supply Voltage
Power Supply Current
Input Resistance
(IN-to-V
T
)
Differential Input Resistance
(IN-to-/IN)
Input HIGH Voltage
(IN, /IN)
Input LOW Voltage
(IN, /IN)
Input Voltage Swing
(IN, /IN)
Differential Input Voltage Swing
|IN-/IN|
Input Voltage Threshold that
Triggers FSI
Output Reference Voltage
Voltage from Input to V
T
Condition
Min
2.375
3.0
Typ
2.5
3.3
60
Max
2.625
3.6
75
55
110
V
CC
V
IH
–0.1
1.0
Units
V
V
mA
Ω
Ω
V
V
V
V
No load, max V
CC
45
90
0.1
0
See Figure 2a. Note 6
See Figure 2b.
0.1
0.2
50
100
30
I
VREF-AC
= + 0.5mA
V
CC
–1.3
V
CC
–1.2
100
V
CC
–1.1
1.28
mV
V
V
March 2007
4
M9999-031307-A
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89846U
LVPECL Outputs DC Electrical Characteristics
(7)
V
CC
= 2.5V ±5% or 3.3V ±10%; R
L
= 50Ω to V
CC
-2V; T
A
= –40°C to + 85°C, unless otherwise stated.
Symbol
V
OH
V
OL
V
OUT
V
DIFF_OUT
Parameter
Output HIGH Voltage
Output LOW Voltage
Output Voltage Swing
Differential Output Voltage Swing
Condition
Q, /Q
Q, /Q
See Figure 2a.
See Figure 2b.
Min
V
CC
-1.145
V
CC
-1.945
550
1100
800
1600
Typ
Max
V
CC
-0.895
V
CC
-1.695
950
Units
V
V
mV
mV
LVTTL/CMOS DC Electrical Characteristics
(7)
V
CC
= 2.5V ±5% or 3.3V ±10%; T
A
= –40°C to + 85°C, unless otherwise stated.
Symbol
V
IH
V
IL
I
IH
I
IL
Note:
7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Parameter
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Condition
Min
2.0
Typ
Max
0.8
Units
V
V
µA
µA
-125
-300
30
March 2007
5
M9999-031307-A
hbwhelp@micrel.com
or (408) 955-1690
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