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K7R323682M-FC20

Description
QDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165
Categorystorage    storage   
File Size211KB,20 Pages
ManufacturerSAMSUNG
Websitehttp://www.samsung.com/Products/Semiconductor/
Download Datasheet Parametric View All

K7R323682M-FC20 Overview

QDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165

K7R323682M-FC20 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerSAMSUNG
Parts packaging codeBGA
package instructionLBGA, BGA165,11X15,40
Contacts165
Reach Compliance Codeunknown
ECCN code3A991.B.2.A
Maximum access time0.45 ns
Other featuresPIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)200 MHz
I/O typeSEPARATE
JESD-30 codeR-PBGA-B165
JESD-609 codee0
length17 mm
memory density37748736 bit
Memory IC TypeQDR SRAM
memory width36
Humidity sensitivity level3
Number of functions1
Number of terminals165
word count1048576 words
character code1000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize1MX36
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeLBGA
Encapsulate equivalent codeBGA165,11X15,40
Package shapeRECTANGULAR
Package formGRID ARRAY, LOW PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)240
power supply1.5/1.8,1.8 V
Certification statusNot Qualified
Maximum seat height1.4 mm
Maximum standby current0.3 A
Minimum standby current1.7 V
Maximum slew rate0.87 mA
Maximum supply voltage (Vsup)1.9 V
Minimum supply voltage (Vsup)1.7 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
width15 mm
Base Number Matches1
K7R323682M
K7R321882M
K7R320982M
K7R320882M
Document Title
Preliminary
1Mx36 & 2Mx18 & 4Mx9 & 4Mx8 QDR
TM
II b2 SRAM
1Mx36-bit, 2Mx18-bit, 4Mx9-bit, 4Mx8-bit QDR
TM
II b2 SRAM
Revision History
Rev. No.
0.0
0.1
History
1. Initial document.
1.
2.
3.
4.
5.
6.
Pin name change from DLL to Doff.
Vddq range change from 1.5V to 1.5V~1.8V.
Update JTAG test conditions.
Reserved pin for high density name change from NC to Vss/SA
Delete AC test condition about Clock Input timing Reference Level
Delete clock description on page 2 and add HSTL I/O comment
Draft Date
June, 30 2001
Dec. 5 2001
Remark
Advance
Preliminary
0.2
1. Update current characteristics in DC electrical characteristics
2. Change AC timing characteristics
3. Update JTAG instruction coding and diagrams
1.
2.
3.
4.
5.
1.
2.
3.
4.
Add 4Mx9 Organization.
Add -FC25 part (Part Number, Idd, AC Characteristics)
Add AC electrical characteristics.
Change AC timing characteristics.
Change DC electrical characteristics(I
SB1
)
Change the data Setup/Hold time.
Change the Access Time.(tCHQV, tCHQX, etc.)
Change the Clock Cycle Time.(MAX value of tKHKH)
Change the JTAG instruction coding.
July, 29. 2002
Preliminary
0.3
Sep. 6. 2002
Preliminary
0.4
Oct. 7. 2002
Preliminary
0.5
1. Change the Boundary scan exit order.
2. Change the AC timing characteristics(-25, -20)
3. Correct the Overshoot and Undershoot timing diagrams.
1. Change the JTAG Block diagram
Dec. 16, 2002
Preliminary
0.6
Dec. 26, 2002
Preliminary
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Dec. 2002
Rev 0.6
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