.
Preliminary
Features
• High Performance:
IBMN312164CT3 IBMN312804CT3
IBMN312404CT3
128Mb Synchronous DRAM - Die Revision B
• Programmable CAS Latency: 2, 3
• Programmable Burst Length: 1, 2, 4, 8
• Programmable Wrap: Sequential or Interleave
• Multiple Burst Read with Single Write Option
• Automatic and Controlled Precharge Command
• Data Mask for Read/Write control (x4, x8)
• Dual Data Mask for byte control (x16)
• Auto Refresh (CBR) and Self Refresh
• Suspend Mode and Power Down Mode
• Standard Power operation
• 4096 refresh cycles/64ms
• Random Column Address every CK (1-N Rule)
• Single 3.3V
±
0.3V Power Supply
• LVTTL compatible
• Package: 54-pin 400 mil TSOP-Type II
-75H
3
-75D
3
-75A, -260, -360, -10,
Units
CL=2 CL=3 CL=3 CL=2 CL=3 CL=3
f
CK
Clock
Frequency
133
7.5
—
5.4
133
7.5
—
5.4
133
7.5
—
5.4
100
10
—
6
100
10
—
6
100
10
7
9
MHz
ns
ns
ns
t
CK
Clock Cycle
t
AC
t
AC
Clock Access
Time
1
Clock Access
Time
2
1. Terminated load. See AC Characteristics on page 37.
2. Unterminated load. See AC Characteristics on page 37.
3. t
RP
= t
RCD
= 2 CKs
• Single Pulsed RAS Interface
• Fully Synchronous to Positive Clock Edge
• Four Banks controlled by BS0/BS1
(Bank Select)
Description
The IBMN312404CT3, IBMN312804CT3, and
IBMN312164CT3 are four-bank Synchronous
DRAMs organized as 8Mbit x 4 I/O x 4 Bank, 4Mbit x
8 I/O x 4 Bank, and 2Mbit x 16 I/O x 4 Bank, respec-
tively. These synchronous devices achieve high-
speed data transfer rates of up to 133MHz by
employing a pipeline chip architecture that synchro-
nizes the output data to a system clock. The chip is
fabricated with IBM’ advanced 128Mbit single tran-
s
sistor CMOS DRAM process technology.
The device is designed to comply with all JEDEC
standards set for synchronous DRAM products,
both electrically and mechanically. All of the control,
address, and data input/output (I/O or DQ) circuits
are synchronized with the positive edge of an exter-
nally supplied clock.
RAS, CAS, WE, and CS are pulsed signals which
are examined at the positive edge of each externally
applied clock (CK). Internal chip operating modes
are defined by combinations of these signals and a
command decoder initiates the necessary timings
for each operation. A fourteen bit address bus
accepts address data in the conventional RAS/CAS
multiplexing style. Twelve row addresses (A0-A11)
and two bank select addresses (BS0, BS1) are
strobed with RAS. Eleven column addresses (A0-
A9, A11) plus bank select addresses and A10 are
strobed with CAS. Column address A11 is dropped
on the x8 device, and column addresses A11 and
A9 are dropped on the x16 device.
Prior to any access operation, the CAS latency,
burst length, and burst sequence must be pro-
grammed into the device by address inputs A0-A11,
BS0, BS1 during a mode register set cycle. In addi-
tion, it is possible to program a multiple burst
sequence with single write cycle for write through
cache operation.
Operating the four memory banks in an interleave
fashion allows random access operation to occur at
a higher rate than is possible with standard DRAMs.
A sequential and gapless data rate of up to 133MHz
is possible depending on burst length, CAS latency,
and speed grade of the device. Auto Refresh (CBR)
and Self Refresh operation are supported.
06K7582.H03335A
01/01
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 66
Preliminary
Pin Description
CK
CKE
CS (CS0, CS1)
RAS
CAS
WE
BS1, BS0
A0 - A11
Clock Input
Clock Enable
Chip Select
IBMN312164CT3 IBMN312804CT3
IBMN312404CT3
128Mb Synchronous DRAM - Die Revision B
DQ0-DQ15
DQM, LDQM, UDQM
V
DD
V
SS
V
DDQ
V
SSQ
NC
—
Data Input/Output
Data Mask
Power (+3.3V)
Ground
Power for DQs (+3.3V)
Ground for DQs
No Connection
—
Row Address Strobe
Column Address Strobe
Write Enable
Bank Select
Address Inputs
Input/Output Functional Description
Symbol
CLK
Type
Input
Polarity
Positive
Edge
Active High
Function
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
Activates the CLK signal when high and deactivates the CLK signal when low. By deactivating the
clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode.
CKE
Input
CS, CS0,
CS1
RAS, CAS,
WE
BS0, BS1
Input
CS (CS0, CS1 for stacked devices) enables the command decoder when low and disables the
Active Low command decoder when high. When the command decoder is disabled, new commands are
ignored but previous operations continue.
Active Low
—
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to
be executed by the SDRAM.
Selects which bank is to be active.
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11) when sam-
pled at the rising clock edge.
During a Read or Write command cycle, A0-A9 and A11 defines the column address (CA0-CA9,
CA11) when sampled at the rising clock edge.
A10 is used to invoke auto-precharge operation at the end of the burst read or write cycle. If A10 is
high, auto-precharge is selected and BS0, BS1 defines the bank to be precharged. If A10 is low,
autoprecharge is disabled.
During a Precharge command cycle, A10 is used in conjunction with BS0, BS1 to control which
bank(s) to precharge. If A10 is high, all banks will be precharged regardless of the state of BS. If
A10 is low, then BS0 and BS1 are used to define which bank to precharge.
Data Input/Output pins operate in the same manner as on conventional DRAMs.
Input
Input
A0 - A11
Input
—
DQ0 - DQ15
Input-
Output
—
DQM
LDQM
UDQM
Input
The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high.
In x16 products, LDQM and UDQM control the lower and upper byte I/O buffers, respectively. In
Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output
Active High
enable. DQM low turns the output buffers on and DQM high turns them off. In Write mode, DQM
has a latency of zero and operates as a word mask by allowing input data to be written if it is low
but blocks the write operation if DQM is high.
—
—
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise immunity.
V
DD
, V
SS
V
DDQ
V
SSQ
Supply
Supply
06K7582.H03335A
01/01
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 3 of 66
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