V54C3256164V-8 datasheet, PDF - EEWORLD Datasheet

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V54C3256164V-8: DescriptionSynchronous DRAM, 16MX16, 6ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54; Categorystorage storage; File Size390KB，48 Pages; ManufacturerMosel Vitelic Corporation ( MVC ); Websitehttp://www.moselvitelic.com

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V54C3256164V-8 Overview

Synchronous DRAM, 16MX16, 6ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54

V54C3256164V-8 Parametric

Parameter Name	Attribute value
Maker	Mosel Vitelic Corporation ( MVC )
Parts packaging code	TSOP2
package instruction	TSOP2,
Contacts	54
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	6 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PDSO-G54
length	22.38 mm
memory density	268435456 bit
Memory IC Type	SYNCHRONOUS DRAM
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	54
word count	16777216 words
character code	16000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	16MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Certification status	Not Qualified
Maximum seat height	1.2 mm
self refresh	YES
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	DUAL
width	10.16 mm
Base Number Matches	1

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MOSEL VITELIC

V54C3256164V

HIGH PERFORMANCE 3.3 VOLT

16M X 16 SYNCHRONOUS DRAM

4 BANKS X 4Mbit X 16

PRELIMINARY

-75

System Frequency (f

)

Clock Cycle Time (t

CK3

)

Clock Access Time (t

AC3

) CAS Latency = 3

Clock Cycle Time (t

CK2

)

Clock Access Time (t

AC2

) CAS Latency = 2

133MHz

7.5 ns

5.4 ns

10 ns

6 ns

-8PC

125 MHz

8 ns

6 ns

10 ns

6 ns

-8

125 MHz

8 ns

6 ns

12 ns

6 ns

Features

4 banks x 4Mbit x 16 organization

High speed data transfer rates up to 133 MHz

Full Synchronous Dynamic RAM, with all signals

referenced to clock rising edge

Single Pulsed RAS Interface

Data Mask for byte Control

Four Banks controlled by BA0 & BA1

Programmable CAS Latency: 2, 3

Programmable Wrap Sequence: Sequential or

Interleave

Programmable Burst Length:

1, 2, 4, 8 and full page for Sequential Type

1, 2, 4, 8 for Interleave Type

Multiple Burst Read with Single Write Operation

Automatic and Controlled Precharge Command

Random Column Address every CLK (1-N Rule)

Suspend Mode and Power Down Mode

Auto Refresh and Self Refresh

Refresh Interval: 8192 cycles/64 ms

Available in 54 Pin 400 mil TSOP-II

LVTTL Interface

Single +3.3 V

0.3 V Power Supply

-75 parts for PC133 3-3-3 operation

-8PC parts for PC100 2-2-2 operation

-8 parts for PC100 3-2-2 operation

Description

The V54C3256164V is a four bank Synchronous

DRAM organized as 4 banks x 4Mbit x 16. The

V54C3256164V achieves high speed data transfer

rates up to 133 MHz by employing a chip architec-

ture that prefetches multiple bits and then synchro-

nizes the output data to a system clock

All of the control, address, data input and output

circuits are synchronized with the positive edge of

an externally supplied clock.

Operating the four memory banks in an inter-

leaved fashion allows random access operation to

occur at higher rate than is possible with standard

DRAMs. A sequential and gapless data rate of up to

133 MHz is possible depending on burst length,

CAS latency and speed grade of the device.

Device Usage Chart

Operating

Temperature

Range

C to 70

Package Outline

•

Access Time (ns)

-75

•

Power

-8

•

-8PC

•

Std.

•

Temperature

Mark

Blank

V54C3256164V Rev. 1.1 January 2000

V54C3256164V-8 Related Products

	V54C3256164V-8	V54C3256164V-75	V54C3256164V-8PC
Description	Synchronous DRAM, 16MX16, 6ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54	Synchronous DRAM, 16MX16, 5.4ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54	Synchronous DRAM, 16MX16, 6ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54
Maker	Mosel Vitelic Corporation ( MVC )	Mosel Vitelic Corporation ( MVC )	Mosel Vitelic Corporation ( MVC )
Parts packaging code	TSOP2	TSOP2	TSOP2
package instruction	TSOP2,	TSOP2,	TSOP2,
Contacts	54	54	54
Reach Compliance Code	unknown	unknown	unknown
ECCN code	EAR99	EAR99	EAR99
access mode	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	6 ns	5.4 ns	6 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
JESD-30 code	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54
length	22.38 mm	22.38 mm	22.38 mm
memory density	268435456 bit	268435456 bit	268435456 bit
Memory IC Type	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM
memory width	16	16	16
Number of functions	1	1	1
Number of ports	1	1	1
Number of terminals	54	54	54
word count	16777216 words	16777216 words	16777216 words
character code	16000000	16000000	16000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C
organize	16MX16	16MX16	16MX16
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSOP2	TSOP2	TSOP2
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm	1.2 mm
self refresh	YES	YES	YES
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	GULL WING	GULL WING	GULL WING
Terminal pitch	0.8 mm	0.8 mm	0.8 mm
Terminal location	DUAL	DUAL	DUAL
width	10.16 mm	10.16 mm	10.16 mm
Base Number Matches	1	1	1

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