Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV)
Data Sheet
Low-Power, Single and Dual-Channel Digital Isolators
Silicon Lab's family of ultra-low-power digital isolators are CMOS devices offering sub-
stantial data rate, propagation delay, power, size, reliability, and external BOM advan-
tages when compared to legacy isolation technologies. The operating parameters of
these products remain stable across wide temperature ranges and throughout device
service life for ease of design and highly uniform performance. All device versions have
Schmitt trigger inputs for high noise immunity and only require V
DD
bypass capacitors.
Data rates up to 150 Mbps are supported, and all devices achieve worst-case propaga-
tion delays of less than 10 ns. Ordering options include a choice of isolation ratings (up
to 5 kV) and a selectable fail-safe operating mode to control the default output state dur-
ing power loss. All products are safety certified by UL, CSA, and VDE, and products in
wide-body packages support reinforced insulation withstanding up to 5 kV
RMS
.
KEY FEATURES
• High-speed operation
• DC to 150 Mbps
• No start-up initialization required
• Wide Operating Supply Voltage:
• 2.6 – 5.5 V
• Up to 5000 V
RMS
isolation
• High electromagnetic immunity
• Ultra low power (typical)
• 5 V Operation:
• < 2.6 mA/channel at 1 Mbps
• < 6.8 mA/channel at 100 Mbps
• 2.70 V Operation:
• < 2.3 mA/channel at 1 Mbps
• < 4.6 mA/channel at 100 Mbps
• Schmitt trigger inputs
• Selectable fail-safe mode
• Default high or low output
• Precise timing (typical)
• 11 ns propagation delay max
• 1.5 ns pulse width distortion
• 0.5 ns channel-channel skew
Applications
•
•
•
•
Industrial automation systems
Medical electronics
Hybrid electric vehicles
Isolated switch mode supplies
•
•
•
•
Isolated ADC, DAC
Motor control
Power inverters
Communication systems
Safety Regulatory Approvals
• UL 1577 recognized
• Up to 5000 V
RMS
for 1 minute
• CSA component notice 5A approval
• IEC 60950-1, 61010-1, 60601-1
(reinforced insulation)
• VDE certification conformity
• IEC 60747-5-5 (VDE0884 Part 5)
• EN60950-1 (reinforced insulation)
• 2 ns propagation delay skew
• 5 ns minimum pulse width
• Transient immunity 45 kV/µs
• AEC-Q100 qualification
• Wide temperature range
• –40 to 125 °C at 150 Mbps
• RoHS compliant packages
• SOIC-16 wide body
• SOIC-8 narrow body
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Rev. 1.4
Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Features List
1. Features List
• High-speed operation
• DC to 150 Mbps
• No start-up initialization required
• Wide Operating Supply Voltage:
• 2.6 – 5.5 V
• Up to 5000 V
RMS
isolation
• High electromagnetic immunity
• Ultra low power (typical)
• 5 V Operation:
• < 2.6 mA/channel at 1 Mbps
• < 6.8 mA/channel at 100 Mbps
• 2.70 V Operation:
• < 2.3 mA/channel at 1 Mbps
• < 4.6 mA/channel at 100 Mbps
• Schmitt trigger inputs
• Selectable fail-safe mode
• Default high or low output
• Precise timing (typical)
• 11 ns propagation delay max
• 1.5 ns pulse width distortion
• 0.5 ns channel-channel skew
• 2 ns propagation delay skew
• 5 ns minimum pulse width
• Transient immunity 45 kV/µs
• AEC-Q100 qualification
• Wide temperature range
• –40 to 125 °C at 150 Mbps
• RoHS compliant packages
• SOIC-16 wide body
• SOIC-8 narrow body
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Rev. 1.4 | 1
Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Ordering Guide
2. Ordering Guide
Table 2.1. Ordering Guide
1,2,3
Ordering Part
Number (OPN)
Si8422AB-D-IS
Si8422BB-D-IS
Si8423AB-D-IS
Si8423BB-D-IS
Si8410AD-D-IS
4
Si8410BD-D-IS
4
Si8420AD-D-IS
4
Si8420BD-D-IS
4
Si8421AD-D-IS
4
Si8421BD-D-IS
4
Si8422AD-D-IS
Si8422BD-D-IS
Si8423AD-D-IS
Si8423BD-D-IS
Number of
Inputs
VDD1 Side
1
1
2
2
1
1
2
2
1
1
1
1
2
2
Number of
Inputs
VDD2 Side
1
1
0
0
0
0
0
0
1
1
1
1
0
0
Maximum
Data Rate
(Mbps)
1
150
1
150
1
150
1
150
1
150
1
150
1
150
Default
Output
State
High
High
High
High
Low
Low
Low
Low
Low
Low
High
High
High
High
5.0 kVrms
–40 to 125 °C
WB SOIC-16
Isolation
Rating
2.5 kVrms
Temp
Range
–40 to 125 °C
Package
Type
NB SOIC-8
1. All devices >1 kV
RMS
are AEC-Q100 qualified.
2. “Si” and “SI” are used interchangeably.
3. All packages are RoHS-compliant with peak solder reflow temperatures of 260 °C according to the JEDEC industry standard clas-
sifications.
4. Refer to Si8410/20/21 data sheet for information regarding 2.5 kV rated versions of these products.
5. An "R" at the end of the part number denotes tape and reel packaging option.
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Functional Description
3. Functional Description
3.1 Theory of Operation
The operation of an Si84xx channel is analogous to that of an opto coupler, except an RF carrier is modulated instead of light. This
simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A simplified
block diagram for a single Si84xx channel is shown in the figure below.
Transmitter
RF
OSCILLATOR
Receiver
A
MODULATOR
Semiconductor-
Based Isolation
Barrier
DEMODULATOR
B
Figure 3.1. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the
Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that
decodes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying
scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to
magnetic fields. See the figure below for more details.
Input Signal
Modulation Signal
Output Signal
Figure 3.2. Modulation Scheme
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Functional Description
3.2 Eye Diagram
The figure below illustrates an eye-diagram taken on an Si8422. For the data source, the test used an Anritsu (MP1763C) Pulse Pattern
Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8422 were captured on an oscilloscope. The re-
sults illustrate that data integrity was maintained even at the high data rate of 150 Mbps. The results also show that 2 ns pulse width
distortion and 350 ps peak jitter were exhibited.
Figure 3.3. Eye Diagram
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Embedded System
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